Intel announces Tri-gate "3-D" transistors for upcoming Ivy Bridge based processors

[Tsavo]

It's worse than we thought. It's bad enough that Intel was paying off Dell and HP to get them to use their CPUs, I wonder what they did to the aliens to prevent them from getting Opterons...

I think they were looking at integer performance and on-paper performance is what led them down the P4 path. No conspiracy here, US dollars can't be spent on other planets and vice versa, so they were stealing the stuff.

Nevertheless, they were coming here to get Athlon X2's when they crashed.

We do suspect they've set up a few shell corporations so they can get our tech without getting shot at by fat security guards. Do folks really think they are buying and giving away free Ipads over the internet? It's all a clever ruse designed to befuddle the unwary. And while the global economy was shrinking, Intel's sales were increasing. This just shows that some parts of Earth's economy aren't in a closed system.

 

[Borealis7]

i'd like to see this technology pass over to GPUs, which need lower voltage the most IMO.

 

[WildW]

Curse you Intel. Now I want some waffles.

 

[tommo123]

so how effective will this process be for atom chips then? anyone able to guess? i mean the chipset also done at this process. that was a weakness with atom right? low power chips being cancelled out by the power draw of the chipset?

 

[Cerb]

so how effective will this process be for atom chips then? anyone able to guess? i mean the chipset also done at this process. that was a weakness with atom right? low power chips being cancelled out by the power draw of the chipset?

No, that was a problem for customers who did not want to do exactly what Intel had planned. I think Intel has a pathological fear of their own products competing with each other, and of not having every market niche served by exactly one distinct product, so they will do things that seem asinine when that may occur, like pair up Atoms with chipsets that aren't low-power, so that the Atom won't look better than their CULV, nor upcoming i3 CPUs (also, the $5-700 ultrathin notebooks with Atoms, because it was more expensive to buy a lone Atom, and higher-power chipset, than to buy an Atom+lower-power chipset combo, but the latter forced netbook form factor restrictions).

 

[jimbo75]

Why do people think immersion lithography provides a performance benefit?

I'm sure most don't. The point was that immersion was a new method and there could be a bonus or drawback from utilising it.

 

[jimbo75]

The nearest star you are referring to is the sun.

 

[Borealis7]

BD's thunder = stolen before its released.
i can already see the last sentence in Anand's BD release article: "with Ivy Bridge just a few months away, Intel has nothing to be worried about."

 

[khon]

Damn, I want one of these.

I'm thinking 13-14 inch laptop, quadcore Ivy Bridge, 120GB SATA-6Gbs SSD, lightweight aluminum body, 10+ hours battery lifetime.

Only question is which manufacturer will put it together for me, and how long I have to wait

 

[khon]

Why do people think immersion lithography provides a performance benefit?

Because it does ?

The smallest linewidth you can do without immersion is ~60nm, with immersion it's ~40nm (for single patterning and dense lines).

 

[Soleron]

BD's thunder = stolen before its released.
i can already see the last sentence in Anand's BD release article: "with Ivy Bridge just a few months away, Intel has nothing to be worried about."

What it it only launches with 2/4 cores? It's not coming to the high-end until 2H '12 and until then the quad-core SB-E will be positioned above it, so I don't see them launching at 6/8. We know 2 and 4 core IB dies exist, so I think it's unlikely they'd do more that two dies for that segment.

 

[Idontcare]

Because it does ?

The smallest linewidth you can do without immersion is ~60nm, with immersion it's ~40nm (for single patterning and dense lines).

Dry-litho can be used in the creation of 40nm lines. Even 25nm. (we had 25nm gate widths with dry-litho all the way back at 65nm)

Litho tech is merely the means to an end, but there are many different means to that same end.

Immersion makes it easier to get to 40nm linewidths (and 25nm) but in and of itself it does not add performance. All the rest of the integration engineering does that. (stress engineering, HKMG selection, source/drain materials, etc)

Whether I use trimmed resist integration from dry-litho printing, trimmed resist integration from immersion-litho, or imprint-litho...the performance of my transistor is entirely dependent on all the other stuff I do to the xtor.

Now I could do resist-trimming rather badly, add lots of LER in the process, and then claim that because of LER I am better off with immersion-litho. But that is more an engineering tradeoff in terms of process development versus time.

There is a reason immersion litho is reserved for use on only the smallest lines (more $$$) and dry-litho with resist trim is still used everywhere else (less $$$). Its not for performance, its just cost management.

 

[khon]

Dry-litho can be used in the creation of 40nm lines. Even 25nm. (we had 25nm gate widths with dry-litho all the way back at 65nm)

I specified dense lines and single patterning, so no you can not create 40nm lines with dry litho.

Or in other words, it's true that you could get similar linewidth with dry lithography and various tricks, but you would not be able to pack as many transistors into the same amount of space.

 

[Borealis7]

IDC got BURNED! no, i have no idea what they're talkin' 'bout either...

 

[Nemesis 1]

What it it only launches with 2/4 cores? It's not coming to the high-end until 2H '12 and until then the quad-core SB-E will be positioned above it, so I don't see them launching at 6/8. We know 2 and 4 core IB dies exist, so I think it's unlikely they'd do more that two dies for that segment.

Man your all over the place. If Ib is only 2/4 cores . Than Intels highend chip would be what 42watts. Than you said earlier intel will likely do more cores rather than go higher clocks . which is it?? A 2 core processor will only be 20 watts . Thats zacata territory. intel could do a single core for 10 watts and be impressive and gain 37% performance improvement on a small chip. I won't use the word but your a sneaky one.

 

[Idontcare]

I specified dense lines and single patterning, so no you can not create 40nm lines with dry litho.

Or in other words, it's true that you could get similar linewidth with dry lithography and various tricks, but you would not be able to pack as many transistors into the same amount of space.

You can specify anything you want, but you did not define what "dense" means to you in this situation. Dense obviously implies a contacted gate density, so what threshold are you implying is the limit?

And more to the point, why bother? It is not answering the question that was asked.

I personally worked with a team of process engineers that routinely made sub-40nm gates without immersion litho and without double-patterning. Obviously the contacted gate pitch was not 160nm, but we still referred to it as "dense" at the time. (It was a 180nm pitch FWIW)

Intel's xtor density, including min-poly pitch, at 45nm is not an outlier relative to that of AMD's.

Intel 45nm 160 nm gate pitch w/dry-litho, AMD 45nm is 190nm gate pitch w/immersion-litho.

(source: RWT)

On the topic of poly scaling: http://www.intel.com/technology/itj/2008/v12i2/5-design/6-evolution.htm

This one is pretty cool: (checkout slide 19) http://ispd.cc/slides11/8.2_Singh.pdf

At any rate you are not addressing the question which was how does immersion litho provide a performance benefit?

 

[khon]

You can specify anything you want, but you did not define what "dense" means to you in this situation. Dense obviously implies a contacted gate density, so what threshold are you implying is the limit?

Dense refers to a pattern with 1:1 line/pitch (sometime also 1:1.3). For example 40nm lines with an 80nm pitch. At least that's what we call it here at ASML. It could be different elsewhere I suppose, though our customers (meaning essentially every fab in the world) all seem to use the same terminology.

At any rate you are not addressing the question which was how does immersion litho provide a performance benefit?

Quite simple really. With immersion litho you can pack more transistors into the same amount of space, so you can fit more of them onto a single chip, and obviously having more transistors means you can do more calculations in a given amount of time (higher performance).

As for linewidth, it is true that there is no real limit, so you could theoretically achieve the same with dry that you can with immersion. You would however have to do a lot of extra tricks to get there, and in the end your pattern quality will be lower.

 

[Idontcare]

Quite simple really. With immersion litho you can pack more transistors into the same amount of space, so you can fit more of them onto a single chip, and obviously having more transistors means you can do more calculations in a given amount of time (higher performance).

That is just a generalized argument for the benefits of shrinking in and of itself, which all litho enabled shrinks accomplish. Whether it is by way of double-pattern, immersion, imprint, EUV, etc.

Intel's 45nm with dry-litho did not suffer performance issues nor xtor density issues.

Where was the performance benefit of immersion litho at 45nm?

 

[khon]

That is just a generalized argument for the benefits of shrinking in and of itself, which all litho enabled shrinks accomplish. Whether it is by way of double-pattern, immersion, imprint, EUV, etc.

Yes it is.

Intel's 45nm with dry-litho did not suffer performance issues nor xtor density issues.

Where was the performance benefit of immersion litho at 45nm?

160nm pitch is not small enough that you need immersion yet. There are still some benefits, like better pattern fidelity, and better depth of focus. But nothing that the consumer would ever notice.

The 22nm process we are discussing in this thread is very different though. They simply could not do that without immersion, and the performance benefits compared to earlier processes based on dry lithography should be obvious.

 

[Idontcare]

Yes it is.

160nm pitch is not small enough that you need immersion yet. There are still some benefits, like better pattern fidelity, and better depth of focus. But nothing that the consumer would ever notice.

You'll get no argument from me regarding the superiority of the cost-benefits results, which is all that I think Phynaz was driving at.

The 22nm process we are discussing in this thread is very different though. They simply could not do that without immersion, and the performance benefits compared to earlier processes based on dry lithography should be obvious.

No argument here either. Although I hope you can admit they could have arrived at the same dimensionality (and performance) by using dry-litho in the form of EUV or nano-imprint or direct ebeam write, albeit at a much higher cost-benefit tradeoff (and would have had to have made it their POR 4 yrs ago so the litho development paralleled their production needs, again at a detriment to the cost-benefit but not a detriment to performance).

Without question immersion-litho is the lowest-cost lowest-risk litho for enabling 22nm design rules. But the dimensions are not unique to immersion-litho, the same performance can be had from other NGL techniques (at a disadvantage to cost-benefits).

I may be speaking out of turn, but I believe that is all that Phynaz was getting at with his question/post.

 

[khon]

You'll get no argument from me regarding the superiority of the cost-benefits results, which is all that I think Phynaz was driving at.

No argument here either. Although I hope you can admit they could have arrived at the same dimensionality (and performance) by using dry-litho in the form of EUV or nano-imprint or direct ebeam write, albeit at a much higher cost-benefit tradeoff (and would have had to have made it their POR 4 yrs ago so the litho development paralleled their production needs, again at a detriment to the cost-benefit but not a detriment to performance).

Without question immersion-litho is the lowest-cost lowest-risk litho for enabling 22nm design rules. But the dimensions are not unique to immersion-litho, the same performance can be had from other NGL techniques (at a disadvantage to cost-benefits).

I may be speaking out of turn, but I believe that is all that Phynaz was getting at with his question/post.

It seems we might agree afterall, and just didn't realize it

 

[Idontcare]

It seems we might agree afterall, and just didn't realize it

It was inevitable We both work in the same industry, only way to reconcile our apparent differences in opinion was to iterate through the vernacular until we identified the gap.

I recognized that I was doing a piss-poor job of expressing the difference between performance and cost-benefit enabled performance. The "vernacular gap" was all on me on this one My bad

Folks here have similar recurring discussions regarding SOI vs. bulk-Si. That too comes down to cost-benefits of upfront R&D cost versus the delayed cost of higher production cost per wafer.

Its the flip-side to dry vs immersion at 45nm. Intel went with the higher production cost double-patterning dry at 45nm (with lower development cost) versus AMD's immersion litho which meant higher development cost (new process tech) but lower production costs relative to double-pattern.

One thing that escapes the attention of many folks when it comes to the discussion of dry vs immersion litho is the mask count and associated costs of added cycle time in the fab.

I was really surprised at TSMC's volume versus lot-count for mask usage. It was made public recently, let me see if I can find that link. It really supported the argument that unless you have extremely high-volume parts on these leading edge nodes the cost of the maskset (which is higher for dry vs litho because of more masks being needed for double-patterning) then ebeam write without masks was the superior cost-benefit approach.

 

[Nemesis 1]

Man this thread got good on this page keep going guys info is flowing like sweet honey

 

[AtenRa]

Since you talking about production costs, Intel says 3D tri-Gate Transistors on 22nm process will add only 2-3% vs ~10% FD-SOI.

The question is, does the FD-SOI provide better characteristics than tri-Gate xtors (Idrive vs less leakage etc) or both technologies provide almost the same but tri-Gate has a lower cost ??

Tri-gate R&D probable had a higher cost than FD-SOI and they probable believe that tri-gate will be useful for more than 2-3 nodes down the road and thats why they chose that technology.

Any thoughts ??

 

[Idontcare]

Since you talking about production costs, Intel says 3D tri-Gate Transistors on 22nm process will add only 2-3% vs ~10% FD-SOI.

The question is, does the FD-SOI provide better characteristics than tri-Gate xtors (Idrive vs less leakage etc) or both technologies provide almost the same but tri-Gate has a lower cost ??

Tri-gate R&D probable had a higher cost than FD-SOI and they probable believe that tri-gate will be useful for more than 2-3 nodes down the road and thats why they chose that technology.

Any thoughts ??

Yeah that is pretty much how these cost-driven decisions are broken down. Do you take the cost up-front and then break it down over many more wafers so you make out ahead in the end, or do you take a lower-cost development path but one in which your per-wafer production costs are higher (but because of your lower-ish volumes, you actually make out ahead in the end that way too).

The SOI vs bulk-Si always made perfect economic sense to me with respect to the companies that use SOI and those who do not. I suspect the situation is similar for FD-SOI.

Why have higher per-wafer production costs if you have large enough production volume to justify investing more on R&D, getting comparable performance, but having slightly lower production costs?

Because of the disparate production volumes between Intel and AMD (GloFo) it makes sense that they manage the economics of R&D versus production costs as they do IMO.