I read about the making of CPU's. From diagram, it seems that the circuits are just "wires". Are there components like transistors, diodes in the core itself? If there are, how are they put in, because i learnt that diodes require two types of material. And by the looks of the difficulty involved in making the circuits, it seems that it is very difficult to put features like diodes in the core.
Inside the CPU
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You might want to start at the Linux documentation project. They have a good explaination of the basics of CPU manufacturing as well as links to more technical information if you need it.
The Linux Documentation Project
The Linux Documentation Project
A cpu is made of several layers... Like an onion. (People who've seen Shrek should get that one. 
)
Anyway, the transistors are built into the substrate of the silicon wafer.
The tips and wells are patterned off in Lithography, and then the silicon wafer is implanted with different ions to change that part of the silicon into either a positive or negative property. This is how they get the "two types of materials".
The transistor gate is then built on top of the previously implanted transistor, and contact pads are built onto the gates.
The first layer of circuits is patterned off in Lithography, and copper (in the case of a Northwood) is deposited to make circuits which interconnect all the millions of transistors. The copper circuits (yes, which essentially are wires) are built up in layers.
At the top of the last layer, several pads are built which will connect to the packaging. Solder bumps are built on top of the pads, and the packaging lines up with the solder when the die is mounted into the packaging.
All this is done on a tiny scale (we could print about 1000 circuits in the width of a human hair), and the smallest particle could cause a die to be inactive. So, a cleanroom is a must. In a Class 1 fab, there is less than one particle (smaller than .5µ in size) per cubic foot of air. Compare that to a hospital which has ~10,000 particles (of undefined size) per cubic foot, and an office which has millions.
The above is obviously a very simplified explanation. There are well over 400 steps in fabricating a working die from a silicon wafer, including insulating between the layers and around the transistors, etching the circuits, polishing the contacts and circuits, planing the insulation flat, etc...
I really like the links below, because they are pretty basic, yet very informative:
How Chips are Made.
What Is a Cleanroom?
How Transistors are Made.
How a Microprocessor Works
If you'd like me to get into further detail (without getting into proprietary information), don't hesitate to ask.
)Anyway, the transistors are built into the substrate of the silicon wafer.
The tips and wells are patterned off in Lithography, and then the silicon wafer is implanted with different ions to change that part of the silicon into either a positive or negative property. This is how they get the "two types of materials".
The transistor gate is then built on top of the previously implanted transistor, and contact pads are built onto the gates.
The first layer of circuits is patterned off in Lithography, and copper (in the case of a Northwood) is deposited to make circuits which interconnect all the millions of transistors. The copper circuits (yes, which essentially are wires) are built up in layers.
At the top of the last layer, several pads are built which will connect to the packaging. Solder bumps are built on top of the pads, and the packaging lines up with the solder when the die is mounted into the packaging.
All this is done on a tiny scale (we could print about 1000 circuits in the width of a human hair), and the smallest particle could cause a die to be inactive. So, a cleanroom is a must. In a Class 1 fab, there is less than one particle (smaller than .5µ in size) per cubic foot of air. Compare that to a hospital which has ~10,000 particles (of undefined size) per cubic foot, and an office which has millions.
The above is obviously a very simplified explanation. There are well over 400 steps in fabricating a working die from a silicon wafer, including insulating between the layers and around the transistors, etching the circuits, polishing the contacts and circuits, planing the insulation flat, etc...
I really like the links below, because they are pretty basic, yet very informative:
How Chips are Made.
What Is a Cleanroom?
How Transistors are Made.
How a Microprocessor Works
If you'd like me to get into further detail (without getting into proprietary information), don't hesitate to ask.
Have seen the movie several times and I just don't get it
Anyway Wingznut pez can you delve into how the crystals are grown that the wafers are cut from?
Ken
Originally posted by: Carrot39
Have seen the movie several times and I just don't get it
Anyway Wingznut pez can you delve into how the crystals are grown that the wafers are cut from?
Ken
i've seen it twice and dont get it.
how do you get something as small as 1/3rd of a transistor to be doped one way while something right next to it is doped another way?
The size of discrete devices like p/n diodes and resistors in ICs are much larger than transistor structures. Thus there are generally few of them incorporated into todays designs unless they are necessary to perform periphery functions such as electrostatic discharge protection or something along those lines. Modern CMOS processing uses self-aligned source and drain wells. This means the wells are defined by the presence of your poly gate. I'll step you through a generic process for a modern transistor.
1) You have your silicon substrate, you remove any native oxide (or as i like to call it CrapOx
) with a cleaning process. You immediately move the wafer into a furnace system (RTA, Batch Furnace, whatever) and grow your high quality gate oxide. 2) A layer of doped polysilicon is blanket deposited over the wafer. So now you have aSilicon/Si02/PolySi sandwich.
3) Using your most advanced lithography you define your poly gate structures with resist. Where your resist remains the poly will not be plasma etched away. Now you have silicon with small rectangular islands of poly-si. Don't forget to strip your resist off, and better give it a clean too because resist scumming can really bite you in the ass
.4) You recoat with resist and perform lithography. There will be two litho steps, one defines your pfets and the other your nfets. These wells are fairly large in comparison to your gate length. You leave resist over all your pfets to start with for example. Then you can do a blanket P or As implant which will define your wells. Now you strip off the resist, recoat, and re-expose to cover up all your nfet structures. Now you can blanket implant with boron.
Now you have a source/gate/drain structure for n and p channel FET transistors. Of course there are many other steps in todays leading edge submicron designs. Features like sidewall spacers, LDD regions, Vt adjusts, punchthru implants, halo implants and other tricks of the trade. I hope that is fairly clear, if not I can try to explain it more/less detail.
I'm not wingznut but silicon ingots are generally grown by the CZ method. Wherein silicon is melted inside of a large quartz crucible. It is generally desireable to have some light doping of starting silicon and at this point impurity sources are added as desired to reach a predetermined resistivity. It should be noted that significant amounts of oxygen is introduced into the silicon from the quartz, this has both beneficial and detrimental attributes. A 'seed' crystal is affixed to the end of a strong metal pull rod. This seed contains the crystalline structure desired of the silicon. As it is inserted into the surface of the melt the molten silicon at the surface begins to cool onto the seed taking on the crystal structure of the seed as it solidifies.
The pull rod rotates and begins to be extracted from the melt at a speed controlled by computer. As it moves away molten silicon tries to adhere and is pulled away from the heat source and thus solidifies itself. Thus more and more silicon forms a solid cylinder. The cylindrical shape comes from the constant rotation. The slower the pull the larger the diameter of the silicon that has time to solidify.
A typical ingot will be grown to the height of a few meters at a fairly constant 200mm or 300mm diameter. (Actually the outside diameter is larger than this as i'll explain in a second) It is interesting to note that the entire 1,000+ pound ingot is suspended from the very thin seed crystal which was less than an inch in diameter. Silicon is very strong in tensile strength. As I said the outside diameter is typically larger than desired. Since the pull process does not produce the consistant circular size desired the entire ingot is polished and ground to be uniformily round and smooth at an exact 200/300mm.
A large saw that has its inside diameter coated with diamonds is used to cut the individual wafers from the ingot, in a somewhat similar fashion to what you see at the deli as they slice your salami
. Typical wafer thickness is on the order of 200 microns. Wafers are then gettered to remove defects from the surface regions where your transistors will be made but that is a topic for another discussion.There's a part where Shrek is trying to explain to Duncan (the donkey) about how deep Ogres are. "We have layers... like onions." No? Ok, nevermind...
Each of those would be doped separately. One would be masked off in Litho and Implanted. Then the resist would be cleaned off, and the other side would be masked off and Implanted.
Nice post, Eskimo!
Here's a pretty good link that talks about making silicon ingots and wafers. (It even has illustrations!)
Nope, they don't. Also, a diamond tipped saw is also what is used for slicing the die out of the wafer.
The physical properties of the silicon lattice structure makes it a surprisingly strong material unless pressure is applied along certain atomic planes in which case wafers will cleave quite easily and cleanly. The categorical term for silicon's lattice structure is the diamond lattice. Named because it shares that structure with a girls' best friend. Just replace the Si atoms with C and you'd have a nice rock to give your significant other
(basically)
So, I talked this quote over with someone else... And neither one of us is sure what that means.
Do you, adlep?
Now to figure out to replace the Si atoms with C atoms
Ok I know this deals with IC's somehow cause they told me so......
Where I used to work and may soon go back to makes Sputtering Targets. How are these used in the CPU manufacturing world?
Thanks
Ken
Ok I know this deals with IC's somehow cause they told me so......
Where I used to work and may soon go back to makes Sputtering Targets. How are these used in the CPU manufacturing world?
Thanks
Ken
Wingznut PEZ, what type of undergraduate/graduate education do you have? Did you take a lot of Electronic Packaging and IC Fabrication courses? Also, is a Lithography Technician an engineer?
Carrot, "Sputtering" is one process of depositing material onto the wafer. I believe the Targets are part of the tool that does the deposition.
(I'll ask the Thin Films guys tomorrow.)
nachiketa1... YGPM.
(I'll ask the Thin Films guys tomorrow.)
nachiketa1... YGPM.
so how much does it cost to prototype a ethenet type router chip which will operate at 5Gbps or 10Gbps?
Originally posted by: Carrot39
Now to figure out to replace the Si atoms with C atoms
Ok I know this deals with IC's somehow cause they told me so......
Where I used to work and may soon go back to makes Sputtering Targets. How are these used in the CPU manufacturing world?
Thanks
Ken
As Wingnut said sputtering (also known as Physical Vapor Deposition) is one form of depositing layers of material onto silicon wafers during various stages of processing. It is most commonly used to apply metals. A sputtering system works by accelerating heavy ions (usually Argon) through use of an electric field. These ions are directed towards the relatively large metal targets which your company makes and impacts upon the surface. The energy of the impact is great enough to overcome the atomic binding energy of the target material and sends those atoms hurtling out into the process chamber. The direction and placement of the components in the chamber ensure that the wafer receives a larger portion of the sputtered material.
There are various techniques used to refine the sputtering process. One addition to a system can be the use a ion beam directed at the target in order to provide additional energy to the surface. This energy decreases the amount of energy the accelerated ions need in order to break loose target atoms. Other design implementations can be used to ensure a uniform and defect free deposition.
The targets themselves are little more than large 8-15" diameter plates of the desired material. They are generally very very pure as that is what is required by semiconductor companies. See link below for a picture.
http://www.nikkomaterials.com/images/semiconductor.jpg
Wingznut,
Only one small addition: the wafers are about 780 microns thick, not 200 microns. For some wire bond products, we grind them down to 430 microns. We were making a product for a costomer that was only 250 microns. The tapers and detapers REALLY didn't like that. We were able to grind down to 90 microns with our tool sets. You could roll those wafers up into a circle!
Sputter/Grinder engineer, Intel Corp.
(I really need to edit my profile)
Only one small addition: the wafers are about 780 microns thick, not 200 microns. For some wire bond products, we grind them down to 430 microns. We were making a product for a costomer that was only 250 microns. The tapers and detapers REALLY didn't like that. We were able to grind down to 90 microns with our tool sets. You could roll those wafers up into a circle!
Sputter/Grinder engineer, Intel Corp.
(I really need to edit my profile)
Yes, you are correct.
(Not that I ever said any different. )
Hey Snooper, send me an email at work... We can chat.
(Not that I ever said any different.
)Hey Snooper, send me an email at work... We can chat.
OOooo.. another Intel worker.... HOw many are there all together in AT? what about in Intel? Why arnt they in AT?
Don't you mean AMD? And there probably are some. They are just being quiet.
There has been some really good posts here Thanks
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