I'm confused about Intels 14nm process lead

[SAAA]

In that case measuring theoretical SRAM size is not sufficient either. Because one process tech could have a very small theoretical SRAM size, but despite this it may be impossible to make use of the high density in practice since the clock speed could be too low (otherwise it would overheat) or it would consume too much power.

In that light of this, transistor density on actual chips using similar functionality blocks and clock speeds ought to be more interesting to compare. TSMC/Apple A8/A8x vs Intel Broadwell U/Y-series should be quite close to compare then? Or do you have some other chips that would result in a more accurate comparison? Maybe AMD Zen on Samsung 14 nm vs Intel desktop Broadwell/Skylake on Intel 14 nm will be better to compare, but they are not out yet unfortunately.

Theoretically SRAM may be denser for 14nm, but real one is similar in the released products, as I said above:

Actually if you compare the SRAM parts of the chips, 4MB L3 for Broadwell and same amount for A8, they are very close in size and density.
But the Broadwell cache runs at almost 3GHz in highest end core-M SKUs and the same exact design is used in 15-28W parts that run up to 3.5GHz... vs 1.5 for Cyclone+? (yeah lower TDP , but by how much? and can it really reach those speeds?)

OK. So much noise for a process that is light years ahead of any other current competitor, and it's not like finfet version of the latters will magically catch this.

About the same size, 6-7mm2 each, but one can run at twice the speed.
I remember a slide somewhere that showed SRAM density of 28 vs 20nm processes and with just a few hunderd MHz more from twice the density increase it crumbled to just 10-20% more...

 

[bronxzv]

I don't think it's been tampered with, other than colorizing it.

http://forums.anandtech.com/showpost.php?p=37159005&postcount=55

 

[III-V]

http://forums.anandtech.com/showpost.php?p=37159005&postcount=55

That's not GT3, though. It's not applicable.

 

[dahorns]

In that case measuring theoretical SRAM size is not sufficient either. Because one process tech could have a very small theoretical SRAM size, but despite this it may be impossible to make use of the high density in practice since the clock speed could be too low (otherwise it would overheat) or it would consume too much power.

In that light of this, transistor density on actual chips using similar functionality blocks and clock speeds ought to be more interesting to compare. TSMC/Apple A8/A8x vs Intel Broadwell U/Y-series should be quite close to compare then? Or do you have some other chips that would result in a more accurate comparison? Maybe AMD Zen on Samsung 14 nm vs Intel desktop Broadwell/Skylake on Intel 14 nm will be better to compare, but they are not out yet unfortunately.

I don't think comparing across designs is going to resolve it either. As has been said, design decisions are a big part of the density calculus. If Intel were to get a higher performing processor in the same footprint as one from a competitor, would we really care if the competitor's processor had more transistors?

Seems to me density is best measured as the functional density for a particular design. Therefore, the best comparator would be the same design built on different processes. We may get a glimpse of that with Intel's Sofia products.

 

[witeken]

Theoretically SRAM may be denser for 14nm, but real one is similar in the released products, as I said above:

About the same size, 6-7mm2 each, but one can run at twice the speed.
I remember a slide somewhere that showed SRAM density of 28 vs 20nm processes and with just a few hunderd MHz more from twice the density increase it crumbled to just 10-20% more...

Yes, you are talking about this slide:

From

http://www.extremetech.com/computin...unts-theyre-a-terrible-way-of-comparing-chips

 

[bronxzv]

That's not GT3, though. It's not applicable.

not decisive, indeed

but my understanding is that TuxDave is nearer to the action than the people who do photoshop jobs like this one with a faked GT3 on the right:

http://images.anandtech.com/doci/8814/Broadwell U Dies.jpg

 

[sm625]

So how come the potential competitors (such as Samsung and TSMC), are so close to 14nm large scale production ?

Because they're always "really close". A year from now they will be "really close". But Intel was never "5 years" ahead anyway. It's more like 2 years in terms of actual transistor density. (TSMC 28nm is basically equivalent to Intel's 22nm, or rather it is closer to Intel's 22nm than it is to Intel's 32nm, even though 28 is mathematically closer to 32 than it is to 22...) But since their SoC designs are lacking, and since windows is so bloated, any process advantage they have is rendered moot.

 

[witeken]

and since windows is so bloated, any process advantage they have is rendered moot.

Most of Intel's tablets run Android. 64-bit.

 

[TuxDave]

I don't think it's been tampered with, other than colorizing it.

The dead space is largely a side-effect of IP reuse for their different die variants. The time spent optimizing that space is better spent creating additional variants.

Except that nothing wants that strip on top. You would have a point if all of a sudden, the GT cores or the system agent in a configuration would be taller than L3$ + IA core. The IA core will not be redesigned to fill up the newly available space.

But based on the die photograph, no one wants it, and so it's either:
1) Just a weird die photograph which includes something that is normally cropped in past die photographs
-or-
2) Hiding something REAL under there (tinfoil hat time!)


Either way, it's either not really there or not usable by the IA/GT/System Agent (because something else is there or they need clearance for die cuts etc...)

 

[TuxDave]

Okay, but he said "it's one the reasons TSMC's yield is worse than Intel's". Didn't TSMC know that 2D would be a bad idea?

Oh, missed the yield part. Sorry. I don't have anything to say about that.

 

[Arachnotronic]

Okay, but he said "it's one the reasons TSMC's yield is worse than Intel's". Didn't TSMC know that 2D would be a bad idea?

AFAIK, 2D routing is "easier" on the design teams, and given that TSMC is a foundry that needs to service design teams of all budgets, 2D routing is the way to go at the expense of yields.

Intel basically services one customer: Intel.

 

[witeken]

Except that nothing wants that strip on top. You would have a point if all of a sudden, the GT cores or the system agent in a configuration would be taller than L3$ + IA core. The IA core will not be redesigned to fill up the newly available space.

But based on the die photograph, no one wants it, and so it's either:
1) Just a weird die photograph which includes something that is normally cropped in past die photographs
-or-
2) Hiding something REAL under there (tinfoil hat time!)


Either way, it's either not really there or not usable by the IA/GT/System Agent (because something else is there or they need clearance for die cuts etc...)

To me it seems it does not exist. If you compare

 

[witeken]

AFAIK, 2D routing is "easier" on the design teams, and given that TSMC is a foundry that needs to service design teams of all budgets, 2D routing is the way to go at the expense of yields.

If you can do 2D, it seems you can also do 1D, so Apple could choose to do it that way if it has a positive impact on yields, right?

Intel basically services one customer: Intel.

Not anymore, but you're right.

 

[imported_ats]

You could argue the same for standardized metrics in most other areas too, but there are reasons we still have them.

And really, none of those reasons apply to process nodes. The people who actually need to know the details and make decisions are quite knowledgeable and intelligent. They don't look at actual node names but instead process parameters. And they always have.

 

[Fjodor2001]

I don't think comparing across designs is going to resolve it either. As has been said, design decisions are a big part of the density calculus. If Intel were to get a higher performing processor in the same footprint as one from a competitor, would we really care if the competitor's processor had more transistors?

Seems to me density is best measured as the functional density for a particular design. Therefore, the best comparator would be the same design built on different processes. We may get a glimpse of that with Intel's Sofia products.

Yes, I agree, but unfortunately we know that will never happen. So we'll have to settle for the best that actually can be achieved. And so far I'd say that would be TSMC 20 nm Apple A8/A8x vs Intel 14 nm Broadwell-Y/U. It will not be optimal, but if Intel 14 nm is far ahead of TSMC, that should show in the transistor density comparison. But apparently it does not.

 

[imported_ats]

Okay, but he said "it's one the reasons TSMC's yield is worse than Intel's". Didn't TSMC know that 2D would be a bad idea?

dual dimensions will always cause some yield loss esp when you are using feature sizes that are below the 1/2 wavelength. As an example, with unidirectional metal, you can quite literally do a static pattern of lines across all designs. It also allows you the advantage to do SADP instead of LELE or LELELE. SADP will have less errors than LELE.

 

[imported_ats]

AFAIK, 2D routing is "easier" on the design teams, and given that TSMC is a foundry that needs to service design teams of all budgets, 2D routing is the way to go at the expense of yields.

Intel basically services one customer: Intel.

The effect on actual design teams of 1D routing is at worse minimal. About the only area it effects is the standard cells (typically and historically for a variety of reasons, layers above the standard cell layers are pretty much 1D at the design level anyways).

 

[imported_ats]

Yes, I agree, but unfortunately we know that will never happen. So we'll have to settle for the best that actually can be achieved. And so far I'd say that would be TSMC 20 nm Apple A8/A8x vs Intel 14 nm Broadwell-Y/U. It will not be optimal, but if Intel 14 nm is far ahead of TSMC, that should show in the transistor density comparison. But apparently it does not.

As has been repeadedly pointed out trans/mm2 is a meaningless metric. For 1, you don't even know if Apple and Intel are using the same definition of an individual transistor! And then we have the whole issue of one design can operate at an Fmax >2x the other design!

 

[Fjodor2001]

As has been repeadedly pointed out trans/mm2 is a meaningless metric.

No that has not been the conclusion, especially if put into context.

For 1, you don't even know if Apple and Intel are using the same definition of an individual transistor!

What? Please tell us what definitions there are.

And then we have the whole issue of one design can operate at an Fmax >2x the other design!

E.g. the Qualcomm Snapdragon 805 operates at 2.65 GHz on TSMC 28 nm. Sorry, Broadwell-U/Y at 14 nm does not operate at 2x2.56=5.12 GHz base frequency, not even turbo. And then we're comparing 28 nm vs 14 nm!

 

[TuxDave]

What? Please tell us what definitions there are.

Pardon the stolen drawings, I would draw some myself but I'm supposed to be working and not arguing on the internet.

Example 1:
Assume this is a minimum size inverter, by simple definition, this takes 2 transistors.
http://users.ecs.soton.ac.uk/bim/notes/cad/guides/gif/inv_stick_ports.gif

Example 2:
If you make the top and transistor twice in height, do you count it as 2 big transistors or 4 small transistors (or 4 fins in finfets)

Example 3:
Now take this:
http://www.ece.unm.edu/~jimp/vlsi/slides/chap5_1-11.gif

If A&B is shorted together and we fixed some other stuff, it's electrically the same thing as the "2x as powerful inverter" Do you count this as two or four transistors?

The concept I keep trying to say is that schematic transistor count is the logical number of transistors required for a gate (inverter is ALWAYS 2). Layout transistor count depends on how you arrange it and your personal rules.

 

[Arachnotronic]

No that has not been the conclusion, especially if put into context.

What? Please tell us what definitions there are.

E.g. the Qualcomm Snapdragon 805 operates at 2.65 GHz on TSMC 28 nm. Sorry, Broadwell-U/Y at 14 nm does not operate at 2x2.56=5.12 GHz base frequency, not even turbo. And then we're comparing 28 nm vs 14 nm!

Haswell can run at ~4.6GHz, and I'd imagine that Broadwell in higher power configurations will be able to run at the same speeds.

Given that the core IP for Broadwell is more or less reused across all of these segments (i.e. Broadwell implemented in Broadwell-EP will probably take up the same die area as Broadwell implemented in Broadwell-ULT), I would say that there is a significant different in Fmax for these designs...about on the order of what you said jokingly

 

[imported_ats]

No that has not been the conclusion, especially if put into context.

There is no possible way you or anyone else will ever get enough context to put anything about trans/mm2 into context to make a valid comparison.

What? Please tell us what definitions there are.

Architected
drawn/synth'd
placed/layedout
post-fractured/litho/actual

and I won't even get into the issues of double sized vs double driven et al.

E.g. the Qualcomm Snapdragon 805 operates at 2.65 GHz on TSMC 28 nm. Sorry, Broadwell-U/Y at 14 nm does not operate at 2x2.56=5.12 GHz base frequency, not even turbo. And then we're comparing 28 nm vs 14 nm!

You might want to actually familiarize yourself with the actual discussion we are having where the actual comparison being made is between an Apple A8 vs Broadwell-U/Y.

 

[Abwx]

Haswell can run at ~4.6GHz, and I'd imagine that Broadwell in higher power configurations will be able to run at the same speeds.

It doesnt work at this frequency, the average limit is about 4.1-4.2GHz, at 14nm they ll surely lose some frequency because of higher thermal density and a process that has not the expected efficency, as said i expect modest frequency for the next DT parts, lower than HW on average.

Given that the core IP for Broadwell is more or less reused across all of these segments (i.e. Broadwell implemented in Broadwell-EP will probably take up the same die area as Broadwell implemented in Broadwell-ULT), I would say that there is a significant different in Fmax for these designs...about on the order of what you said jokingly

Same process than for Core M will be used for the soon to be released parts, this has been stated by the CEO, there will be no difference in Fmax other than the one due to thermal capabilities of the die.

 

[SOFTengCOMPelec]

I'm not sure I agree. We have common standards and definitions in many (or most actually) other technical areas, even though it does not strictly reduce cost.

Just to name a few: SPECint, Gflops, display contrast and brightness, display color space, disk IOPS, the list could be made huge...

As you just said, there are many, many defined/measurable/accurate standards/metrics/specifications in the technical world.

But there are also a number of such things, which are generally agreed to be "too un-measurable/arbitrary" to bolt down, in way of a standardized measurement. Even if such a standard, use to exist.

For example, it would be really nice to know the total number of equivalent logic gates, available on the different, FPGAs, but because there are big differences in the number of usable logic gates, depending on the specific design that you want implemented, and architectural differences, that such specifications, are usually omitted on modern FPGAs.

Benchmarks offer fairly widely differing results, across different architectures, and have plenty of room for manipulation of the results. Making them less suitable for doing what they were originally intended to do.

(I'm NOT an expert Physicist, so could easily be wrong) I think, even what we consider to be standardized SI physics units/measurements, become blurry and indistinct, at the very small (quantum) level.
E.g. A SINGLE electron is traveling down a wire. So there is ONE, and only ONE electron, Yes ?
NO, not at the quantum level, because single electrons, can actually move, as if there was a second electron, near it.

Because they're always "really close". A year from now they will be "really close". But Intel was never "5 years" ahead anyway. It's more like 2 years in terms of actual transistor density. (TSMC 28nm is basically equivalent to Intel's 22nm, or rather it is closer to Intel's 22nm than it is to Intel's 32nm, even though 28 is mathematically closer to 32 than it is to 22...) But since their SoC designs are lacking, and since windows is so bloated, any process advantage they have is rendered moot.

It would be so much easier to compare Intel, to Samsung/TSMC etc, if they were selling broadly similar items, at the top end.

But since Intel currently commands, the bulk of the server chip market (especially the higher end), and the majority of the higher end desktop chips, it is much harder to compare the parts.

Comparing the parts at the lower end of the market, maybe unfair/inaccurate, because we are trying to determine, who is in front, and by how many years.

2 years, sounds way too short a lead to me (my opinion), i.e. I think Intel has a much bigger lead time, than that (gut feeling).

 

[elemein]

On a semi-related topic; Im confused about transistors as a whole.

Like I get what a MOSFET transistor looks like, I know FinFET's, planar, SOI, etc. etc. al that stuff. I get how a single transistor works, but I dont understand how several transistors work together and stuff outside of that. Anyone have any sources?

I already tried reading tons of Anand stuff on it and watched videos, etc. but I'm clearly missing a lot. Anyone have any good resources to learn of this stuff?