i7-3770K vs. i7-2600K: Temperature, Voltage, GHz and Power-Consumption Analysis

[Magic Carpet]

Getting rid of the thick CPU TIM (regardless what CPU TIM used) by reducing the gap height is what is key to reducing the temperatures (and thus power consumption) in these Ivy Bridge chips.

Do you reckon, the Ivy Bridge processors are more likely to have thermal interface issues in the course of the next 10-15 years? Or is it dry-proof?

 

[Engineer]

I didn't read all of this but was overly impressed with the presentation and amount of work. I just chimed in to give a :thumbsup: on that alone! :biggrin:

 

[MrK6]

Great read! Well done as always IDC. :thumbsup:

 

[tweakboy]

This is freakin amazing thread. Wow who wrote this scientist anand gurus ?

The way it look that temp of 100c only @ 3.2Ghz is no good.... even Ivy went to 100c , wtf,,,,, you shouldn't go near 80c imo on these chips... gl

 

[Idontcare]

^ thanks for all the kind words folks, :$, glad you enjoyed the thread!

Do you reckon, the Ivy Bridge processors are more likely to have thermal interface issues in the course of the next 10-15 years? Or is it dry-proof?

When I scraped the original stock CPU TIM off of my IB CPU and from the underside of the IHS it very much had the consistency of one of those thermal-mat pads that get used in laptops and such.

It had every appearance of being very durable and not likely to be going anywhere anytime soon.

I even attempted to reconstitute the stock CPU TIM so I could test it as a HSF TIM, but my efforts failed as the stuff simply was not agreeing with the notion of being soluble in IPA (and I wasn't about to try anything less human-friendly given that my two children and wife occupy the same house )

Based on my experience with this stuff, I'd say (1) it has comparable thermal conductivity properties to that of NT-H1 and MX-4, (2) it is essentially a solid-pad that is not going to dry out (it is already "dried out") or get squeezed out from the so-called pump-out effect.

(incidentally, IC Diamond claims it was designed for and proven to prevent the pump-out effect, I have not verified if this is true for our application though)

 

[BoFox]

RE:

Interesting - looks like there's still nearly 1 watt of leakage per degree C at the highest voltage at 4 GHz.

That's about 2x better than 45nm when I saw about 40W for 20 degrees at 4GHz with my lapped IFX-14, but then again the 3770K is still puny by comparison when running at only 4GHz - although the voltage was pretty high.

 

[Idontcare]

Yeah the static power was marginally improved with 22nm over 32nm, not too surprising considering that with the node shrink all the dielectric insulating layers got thinner.

Ordinarily we would have expected leakage to get worse, not better, but the Finfets really helped with that.

What really saved 22nm from a static leakage perspective is that Intel was able to scale-down the voltage needed to hit any given clockspeed. (clockspeed is not a factor in static leakage, only temperature and voltage are factors in static leakage)

 

[BoFox]

Yeah the static power was marginally improved with 22nm over 32nm, not too surprising considering that with the node shrink all the dielectric insulating layers got thinner.

Ordinarily we would have expected leakage to get worse, not better, but the Finfets really helped with that.

What really saved 22nm from a static leakage perspective is that Intel was able to scale-down the voltage needed to hit any given clockspeed. (clockspeed is not a factor in static leakage, only temperature and voltage are factors in static leakage)

Hmm - I do agree, but still.. clockspeed also increases power consumption almost exactly linearly, so there could be a bit greater leakage associated with more dissipation - unless you keep the temperature (which in turn has a direct relationship with leakage) completely static also, I guess.. so, you're right with the wording after all.

Great work, btw! That is truly amazing!

 

[Hulk]

This "post" need to be turned into an article in the main site I think so that it doesn't drift into non-existence. It should remain as a searchable document in Anandtech.

 

[Harpocrates]

That was a very enjoyable read, although the math was beyond me. How long did it take to compile all the data points?

 

[Idontcare]

That was a very enjoyable read, although the math was beyond me. How long did it take to compile all the data points?

Just a few weeks, two months at the most. I can't really remember the exact timeline at this point but it wasn't something that happened over a weekend