Haswell 4c8t @2.6 Fritz Chess Benchmark <Update:2.8G Haswell>

[CHADBOGA]

This again is not an AMD vs. Intel who is better thread. We are talking about Haswell performance, not AMD and Intel's R&D.


If you want to have a VS discussion go find a thread from 2006.

Shouldn't you be directing your comment at the person who made the AMD vs Intel comparison in the first place in this thread?

 

[Abwx]

If the Haswell chip is running 2.6GHz then I doubt turbo is enabled.

But speed step is enabled since CPUZ show 798mhz frequency.

Are Speedstep and Turbo two separately enabled features ?

 

[Rvenger]

Shouldn't you be directing your comment at the person who made the AMD vs Intel comparison in the first place in this thread?

I meant to add him into the quotes. Ill just remove all my quotes. lol

Thanks for the heads up.

 

[inf64]

@Durvelle27

You score is at stock or OCed? Looks a bit high to be @ 2.6Ghz
Well this benchmark is FP intensive so it's 4 fp units vs 4 fp units in case of i7 and FX8xxx.

 

[Idontcare]

But speed step is enabled since CPUZ show 798mhz frequency.

Are Speedstep and Turbo two separately enabled features ?

They are two seperate features. Its the same with AMD too, you can disable turbo but keep CnQ enabled.

 

[Durvelle27]

@Durvelle27

You score is at stock or OCed? Looks a bit high to be @ 2.6Ghz
Well this benchmark is FP intensive so it's 4 fp units vs 4 fp units in case of i7 and FX8xxx.

nope OC'd XD

 

[Nemesis 1]

There was also 2 other benchmarks previously, and combined with this look a little, well, underwhelming. I was expecting much more. As said, maybe other benchmarks will show better results.

If its all the same lets not combine other benchies that are questionable . I know this is alot to ask of you . But please try to man up.

 

[Nemesis 1]

This again is not an AMD vs. Intel who is better thread. We are talking about Haswell performance, not AMD and Intel's R&D.


If you want to have a VS discussion go find a thread from 2006.

It was you who brought AMD into this discussion . Now you want to bail. My mistake it was mac who walked on hollowed ground

 

[Nemesis 1]

Man I am sleeping . It was the OP that introduced AMD to this topic on the first post .

I little disappointed in only a 10% gain . was looking for at least 15% maybe 20%

 

[Hypertag]

Man I am sleeping . It was the OP that introduced AMD to this topic on the first post .

I little disappointed in only a 10% gain . was looking for at least 15% maybe 20%

10.6% over Ivy (Which had about 5% over sandy) is pretty good. This isn't AVX2 optimized or anything.

 

[Rvenger]

It was you who brought AMD into this discussion . Now you want to bail. My mistake it was mac who walked on hollowed ground

lol, how would it be me when I didn't post above what you quoted?

 

[cytg111]

I take it that Fritz is multi-multi threaded application, if so, we have no idea what those 10% are made up of, some IPC, some TX, some ??. Point being, we cant expect singlethreaded performance to increase 10%.

 

[Greenlepricon]

Not too shabby! Now I'm just wondering how high Haswell will clock. If it oc's like Sandy Bridge then there should be some nice performance from it.

 

[ShintaiDK]

Are Speedstep and Turbo two separately enabled features ?

Yes, very different.

 

[ShintaiDK]

I take it that Fritz is multi-multi threaded application, if so, we have no idea what those 10% are made up of, some IPC, some TX, some ??. Point being, we cant expect singlethreaded performance to increase 10%.

TSX doesnt work on old code either.

Plus I dont even think an application like Fritz can benefit from TSX at all if recoded to use it.

 

[piesquared]

If its all the same lets not combine other benchies that are questionable . I know this is alot to ask of you . But please try to man up.

I don't find the other benchmark all that questionable. Maybe this benchmark is questionable lol

 

[MisterMac]

Are most people "happy" with a 14-15% RAW IPC Increase from haswell over SB on legacy code?


Damn.

I'm not.

Unless MT gains are heavily better - i'm disappointed.

And i didn't mean to start of a intel vs AMD thing - i just made a small jab at how projected peformance for SR would suddenly make them performance kings in one "fix up" generation.

Clearly people can't take jest atm - my bad.

 

[inf64]

Well first we know nothing of actual SR performance and 2nd this is just an ES of Haswell . Simply there is not enough data to make any relevant performance comparison between these 2 cores for the time being.

 

[MisterMac]

Well first we know nothing of actual SR performance and 2nd this is just an ES of Haswell . Simply there is not enough data to make any relevant performance comparison between these 2 cores for the time being.

Hopefully not!

But it's still a relative indication of Legacy code performance.
And i would have preferred just a little more oomph out of that.


I know it's a weird mindset - but i sort of expect Intel to move both in the complex arena for computation and the legacy way.

IMHO, i'm all for Intel being the big bad untoucheable giant - as long as they deliver each generation - but they gotta deliver.

None of this incremental shit on a tock

 

[Idontcare]

I take it that Fritz is multi-multi threaded application, if so, we have no idea what those 10% are made up of, some IPC, some TX, some ??. Point being, we cant expect singlethreaded performance to increase 10%.

Doesn't TX require the code to be re-compiled to take advantage of the hardware feature?

Intel does expect single-threaded performance to increase some 10% though, so its not like we've seen anything here that wasn't to be expected.

 

[ShintaiDK]

Doesn't TX require the code to be re-compiled to take advantage of the hardware feature?

Yep, comes in 2 versions as well.

http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell

Plus the usual restrictions, even when coded for TSX in eitehr HLE or RTM mode.

Intel TSX targets a certain class of shared-memory multi-threaded applications; specifically multi-threaded applications that actively share data. Intel TSX is about allowing programs to achieve fine-grain lock performance without requiring the complexity of reasoning about fine-grain locking.

However, if there is high data contention the algorithm would need to change in order to have an opportunity for high scalability. There are no magic bullets that can solve the problem, since true high data contention implies that the algorithm is effectively serialized.

 

[ShintaiDK]

Are most people "happy" with a 14-15% RAW IPC Increase from haswell over SB on legacy code?

I think its quite good, considering how hard it is to actually increase IPC without new instructions.

If AVX(1) is heavily used tho, Haswell will be alot faster than 10-15%.

I mainly see Haswell as a new major step forward. Vector of all previous scalar instructions plus gather and 256bit with single cycle execution.

Its essentially a giant leap, you just need to have the proper code for it. But it does somewhat suffer the chicken or the egg scenario, specially with AVX2.

 

[ChronoReverse]

Weren't most of the generation jumps since Core 2 around the same level?

 

[ShintaiDK]

Weren't most of the generation jumps since Core 2 around the same level?

Core 2 was only around 20% over Core as well. So you would need to go even further back.

All major boosts essentially only comes from new instructions.

It was all fun and easy as long as you could increase the power budget to the sky.

 

[Idontcare]

I think its quite good, considering how hard it is to actually increase IPC without new instructions.

If AVX(1) is heavily used tho, Haswell will be alot faster than 10-15%.

I mainly see Haswell as a new major step forward. Vector of all previous scalar instructions plus gather and 256bit with single cycle execution.

Its essentially a giant leap, you just need to have the proper code for it. But it does somewhat suffer the chicken or the egg scenario, specially with AVX2.

Really I am impressed they found an extra 10% that apparently Sandy/Ivy Bridge left on the table. Considering how good those chips are, to come in over the top of that with another 10% IPC is darn good.

Just makes me wonder what lengths they are going to have to go to in order to keep finding another 10% and then another 10% going forward. Pollack's rule and all that.