Question Greatest x86 innovations?

[Hulk]

What do you think were the greatest x86 innovations since the inception of the original 8086?

I'm leaning towards macro-ops that were introduced with the original Pentium. The Power PC with its RISC architecture was coming on strong around this time and I'm not sure without macro-ops x86 could have managed to compete with it?

I also remember the 8086 virtual mode with the 386 as being a big deal at the time.

 

[gdansk]

Adding 8 more general purpose registers

 

[Schmide]

protected mode - 386 (not the 286 that was just awkward) virtual memory, flat addressing, descriptor tables, etc. task segments not so much.

AMD64 - (x86-64 EMT64) moved the isa forward with very little downside if any

 

[SarahKerrigan]

What do you think were the greatest x86 innovations since the inception of the original 8086?

I'm leaning towards macro-ops that were introduced with the original Pentium. The Power PC with its RISC architecture was coming on strong around this time and I'm not sure without macro-ops x86 could have managed to compete with it?

I also remember the 8086 virtual mode with the 386 as being a big deal at the time.

OoO - PPro was one of the first truly OoO microarchitectures (especially since Thunder/Lightning didn't ship)

SMT - I believe Northwood (?) was the first shipping SMT uarch anywhere, though IBM had been doing CGMT in the PPC AS stuff for a minute

 

[Hulk]

Interesting, so we have...

Macro-ops with the Pentium
OoO with Pentium Pro (this is a big one)
SMT with Pentium Northwood
AMD 64 (x86-64 EMT64) - I don't know CPU that introduced it?
386 Protected mode, virtual memory (probably the start of the blue screens of death in their day as programmers got lazy and apps started stepping on one another!)
Addition of 8 additional General Purpose Registers - CPU?

It's fun to go back and see where we came from.

 

[naukkis]

protected mode - 386 (not the 286 that was just awkward) virtual memory, flat addressing, descriptor tables, etc. task segments not so much.

Actually 386 protected mode is just same as 286, just expanded to 32bits, with paging unit added. 386 just allows misusing it's segmentation by allowing overlapping segments - which can be as big as addressable memory. It sure makes programming easier but that's actually a shame because 286/386 segmentation is very good memory managing hardware almost without performance disabilities. If there's something designed really well in x86 it's that 386 memory segmentation unit - which was pretty much unused whole 32-bit era and mostly removed from 64-bit x86. It's a shame that pretty much optimally designed hardware did not used because programmers preferred simpler models - though memory protection that segmentation done right actually makes programming easier as it will protect against memory leaks that are extremely hard to make bulletproof without hardware support.

 

[gdansk]

Interesting, so we have...

Macro-ops with the Pentium
OoO with Pentium Pro (this is a big one)
SMT with Pentium Northwood
AMD 64 (x86-64 EMT64) - I don't know CPU that introduced it?
386 Protected mode, virtual memory (probably the start of the blue screens of death in their day as programmers got lazy and apps started stepping on one another!)
Addition of 8 additional General Purpose Registers - CPU?

It's fun to go back and see where we came from.

AMD64 included the extra registers. First appeared in K8 which shipped as Opteron and later Athlon 64.

I was joking a bit chosing a singular feature of x64 as a big change. K8 was probably the most innovative design since P6/Pentium Pro.

 

[adroc_thurston]

Glueless MP with Hypertransport as introduced by K8.

 

[Hulk]

Okay, here's the update.

Macro-ops with the Pentium
OoO with Pentium Pro (this is a big one for me)
SMT with Pentium Northwood
386 Protected mode, virtual memory
Addition of 8 additional General Purpose Registers - First appeared in K8 which shipped as Opteron and later Athlon 64
Glueless MP with Hypertransport as introduced by K8

 

[adroc_thurston]

Okay, here's the update.

Macro-ops with the Pentium
OoO with Pentium Pro (this is a big one for me)
SMT with Pentium Northwood
386 Protected mode, virtual memory
Addition of 8 additional General Purpose Registers - First appeared in K8 which shipped as Opteron and later Athlon 64
Glueless MP with Hypertransport as introduced by K8

Opcache too. In Sandy Bridge.

 

[FelixDeCat]

Opcache too. In Sandy Bridge.

Im using Sandy Bridge as I type this.

It has a built in math co-processor.

 

[SarahKerrigan]

AMD64 included the extra registers. First appeared in K8 which shipped as Opteron and later Athlon 64.

I was joking a bit chosing a singular feature of x64 as a big change. K8 was probably the most innovative design since P6/Pentium Pro.

Was it, though? My recollection is that the core itself is largely a tweaked K7, extended to 64b.

 

[Hulk]

Macro-ops with the Pentium
OoO with Pentium Pro (this is a big one for me)
SMT with Pentium Northwood
386 Protected mode, virtual memory
Addition of 8 additional General Purpose Registers - First appeared in K8 which shipped as Opteron and later Athlon 64
Glueless MP with Hypertransport as introduced by K8
Addition of 1536 entry micro-op for decoded instructions in Sandy Bridge

 

[Tuna-Fish]

OoO - PPro was one of the first truly OoO microarchitectures (especially since Thunder/Lightning didn't ship)

Huh? The first OoO CPUs were built in the mid-60's. Intel could build PPro as it existed because all of the techniques in it had been described previously by CDC and IBM patents, and were already old enough to be out of patent protection.

 

[SarahKerrigan]

Huh? The first OoO CPUs were built in the mid-60's. Intel could build PPro as it existed because all of the techniques in it had been described previously by CDC and IBM patents, and were already old enough to be out of patent protection.

I admit that I had kind of forgotten the Model 91, but calling the CDC 6600 OoO is a stretch.

I can amend to "first truly OoO microprocessor microarchitectures" if you prefer.

 

[Tuna-Fish]

I admit that I had kind of forgotten the Model 91, but calling the CDC 6600 OoO is a stretch.

I can amend to "first truly OoO microprocessor microarchitectures" if you prefer.

Nx586? PPC 603? And I'm pretty sure there was some SPARC one too.

PPro wasn't the first anything. What it was was a very effective implementation using the instruction set that provided backwards compatibility with the legacy software that people wanted to run. I still remember the mid-90's, all the RISC stuff was going OoO before x86 and PPro shocked everyone not because it was first, but because people had expected that cost-effective, fast OoO on x86 would be too hard and so RISC would win. Intel proved everyone wrong.

 

[Hulk]

Huh? The first OoO CPUs were built in the mid-60's. Intel could build PPro as it existed because all of the techniques in it had been described previously by CDC and IBM patents, and were already old enough to be out of patent protection.

This thread is about innovations as they occurred in x86 architecture.

 

[SarahKerrigan]

Nx586? PPC 603? And I'm pretty sure there was some SPARC one too.

PPro wasn't the first anything. What it was was a very effective implementation using the instruction set that provided backwards compatibility with the legacy software that people wanted to run. I still remember the mid-90's, all the RISC stuff was going OoO before x86 and PPro shocked everyone not because it was first, but because people had expected that cost-effective, fast OoO on x86 would be too hard and so RISC would win. Intel proved everyone wrong.

The SPARC one was Thunder/Lightning. Metaflow. I already mentioned it and it never shipped. Sun was institutionally resistant to OoO (they literally never shipped an OoO SPARC until after the Oracle acquisition) - Fujitsu/Amdahl was less so but I don't think they ever shipped an OoO SPARC before Intel did with the PPro. (If so, it was just barely; I think the SPARC64 was the first and only hit mass availability in 96-97. But that's before my time.)

I confess I forgot the Nx586 and probably misjudged the timing of the 603. Mea culpa.

 

[Hulk]

The SPARC one was Thunder/Lightning. Metaflow. I already mentioned it and it never shipped. Sun was institutionally resistant to OoO (they literally never shipped an OoO SPARC until after the Oracle acquisition) - Fujitsu/Amdahl was less so but I don't think they ever shipped an OoO SPARC before Intel did with the PPro. (If so, it was just barely; I think the SPARC64 was the first and only hit mass availability in 96-97. But that's before my time.)

I confess I forgot the Nx586 and probably misjudged the timing of the 603. Mea culpa.

Pentium Pro was the first Pentium II

 

[Thibsie]

Mmm K5 out of order execution based on a RISC core (5 ALU according to Wikipedia but I doubt that).

 

[NTMBK]

SSE with the Pentium III was a pretty big improvement. It brought SIMD, which was nice, but the real big improvement was a scalar floating point instruction set that wasn't complete trash. No need to deal with the weird nonsense of x87 any more!

 

[Mopetar]

Vector processing/instructions in general is a pretty good inclusion IMO. It just took a while for them to get good from an ISA perspective. MMX and 3DNow! were both clunky as you point out.

SSE was a big step up, but I think Sandy Bridge with AVX was where it got really good. Even though SSE was a step up from MMX, it still had a few design oddities that AVX would cure.

 

[Schmide]

AVX was lacking and thusly it only lasted a couple years. AVX2 (haswell) was where things settled. Recently it was declared as the next dividing line for modern OSs x86-64-v3 (AVX2, FMA, MOVEB, bits).

 

[zir_blazer]

SMT/HT was already present in Willamatte die, but only enabled in Foster MP Xeons codenamed as Jackson Technology.

SSE with the Pentium III was a pretty big improvement. It brought SIMD, which was nice, but the real big improvement was a scalar floating point instruction set that wasn't complete trash. No need to deal with the weird nonsense of x87 any more!

3DNow predates SSE and served the same purpose. No idea if SSE is inherently better or just got mainstream because both Intel and AMD supported it whereas 3DNow was AMD only.
K6-2 were know to suck at FPU but with 3DNow they could perform at Pentium 2 levels. There was a port of Quake 2 optimized with 3DNow that did exactly that, literally twice the performance.

 

[NTMBK]

SMT/HT was already present in Willamatte die, but only enabled in Foster MP Xeons codenamed as Jackson Technology.


3DNow predates SSE and served the same purpose. No idea if SSE is inherently better or just got mainstream because both Intel and AMD supported it whereas 3DNow was AMD only.
K6-2 were know to suck at FPU but with 3DNow they could perform at Pentium 2 levels. There was a port of Quake 2 optimized with 3DNow that did exactly that, literally twice the performance.

3DNow was still aliased on the x87 registers, and weren't a full replacement for x87 in scalar code. SSE is a complete replacement, and x64 compilers now basically never generate x87 code.