Global Foundries 32nm Process Status

[Joepublic2]

I had a little birdie tell me that a big part of the reason that the current bulldozer stepping is so underperforming is because AMD is having to fix a lot of process/yield problems at the firmware/microcode level (having to take slower paths for certain instructions and increase latency on lots of buffers/caches due to signal integrity issues etc.) and that an improved process and new stepping could dramatically improve bulldozer's performance characteristics. Anybody care to comment?

 

[sandorski]

Wouldn't surprise me, but I know exactly 0 about that stuff.

 

[BallaTheFeared]

I had a little birdie tell me that a big part of the reason that the current bulldozer stepping is so underperforming is because AMD is having to fix a lot of process/yield problems at the firmware/microcode level (having to take slower paths for certain instructions and increase latency on lots of buffers/caches due to signal integrity issues etc.) and that an improved process and new stepping could dramatically improve bulldozer's performance characteristics. Anybody care to comment?

Too late to matter now, however it would be nice if we could see some drastic improvements all around with Piledriver.

Piledriver vs IB.. AMD is talking about a 10% gain, hopefully that was before they figured out the chip wasn't very good. Intel is talking about 19% TDP decrease, 100MHz clock increase, and pretty lofty gains... Including a 17% increased in CPU score in 3DMark Vantage.

Then what though?

Intel is coming out with ANOTHER new design in less than a year and a half...

 

[soccerballtux]

I had a little birdie tell me that a big part of the reason that the current bulldozer stepping is so underperforming is because AMD is having to fix a lot of process/yield problems at the firmware/microcode level (having to take slower paths for certain instructions and increase latency on lots of buffers/caches due to signal integrity issues etc.) and that an improved process and new stepping could dramatically improve bulldozer's performance characteristics. Anybody care to comment?

and here we go again, hoping that the next thing AMD does will be better...I refuse to get my hopes up it's too depressing!!!

 

[Idontcare]

I had a little birdie tell me that a big part of the reason that the current bulldozer stepping is so underperforming is because AMD is having to fix a lot of process/yield problems at the firmware/microcode level (having to take slower paths for certain instructions and increase latency on lots of buffers/caches due to signal integrity issues etc.) and that an improved process and new stepping could dramatically improve bulldozer's performance characteristics. Anybody care to comment?

Interesting.

But Bulldozer is not clockspeed limited, as evidenced by the 8.4GHz world records...it is power limited. The FX8170 does not exist yet because the FX-8150 at its anemic 3.6GHz already uses way to much power.

The other thing about this line of thinking is that it doesn't explain the performance (IPC) at lower clockspeeds where such fixes would not be necessary.

Take the Interlagos Opteron line, where high clockspeeds were never going to be the focus, why would they ever castrate IPC on those low clockspeed processors just to address a signal integrity issue that limits clockspeeds?

Everywhere we look, be it Llano and its clockspeed enveloped versus power-consumption, to Interlagos, to Zambezi, the "problem" in all cases is IPC/watt. The fundamental microarchitecture itself has too low of IPC, combined with GloFo's 32nm process being a bit of a power-hog.

The parallels between Intel and Prescott vs Dothan on 90nm are there, every where we look.

It would be super-neat if it is true and somehow the magic inside bulldozer has yet to be unlocked. It would be unprecedented too, which would make it even neater.

But it seems odd they would limit performance of ALL bulldozer SKU's just so they could get a few to bin out at 3.6GHz speeds with lowered IPC. And it still doesn't address the fact that the power usage, regardless the performance, is what limits the clockspeeds. The process does not seem to be limiting clockspeeds since they can be clocked to 8GHz if cooled. (which is not true of say Sandy Bridge which doesn't really OC any better if it is cooled)

But I like hope, so here's to hoping for something awesome coming down the pipe for all of us!

 

[podspi]

It really makes you wonder what they were thinking...

Were they expecting the process to be significantly better than it turned out to be?

Were they expecting IPC to be much higher, and then it just wasn't?

Given the length of time BD was in development, I'm still holding out hope that it can be 'fixed'. I'm not expecting magic, but I find it hard to believe that something horrible didn't just go wrong.

Of course, counterpoint is the P4.

 

[Martimus]

Interesting.

But Bulldozer is not clockspeed limited, as evidenced by the 8.4GHz world records...it is power limited. The FX8170 does not exist yet because the FX-8150 at its anemic 3.6GHz already uses way to much power.

The other thing about this line of thinking is that it doesn't explain the performance (IPC) at lower clockspeeds where such fixes would not be necessary.

Take the Interlagos Opteron line, where high clockspeeds were never going to be the focus, why would they ever castrate IPC on those low clockspeed processors just to address a signal integrity issue that limits clockspeeds?

Everywhere we look, be it Llano and its clockspeed enveloped versus power-consumption, to Interlagos, to Zambezi, the "problem" in all cases is IPC/watt. The fundamental microarchitecture itself has too low of IPC, combined with GloFo's 32nm process being a bit of a power-hog.

The parallels between Intel and Prescott vs Dothan on 90nm are there, every where we look.

It would be super-neat if it is true and somehow the magic inside bulldozer has yet to be unlocked. It would be unprecedented too, which would make it even neater.

But it seems odd they would limit performance of ALL bulldozer SKU's just so they could get a few to bin out at 3.6GHz speeds with lowered IPC. And it still doesn't address the fact that the power usage, regardless the performance, is what limits the clockspeeds. The process does not seem to be limiting clockspeeds since they can be clocked to 8GHz if cooled. (which is not true of say Sandy Bridge which doesn't really OC any better if it is cooled)

But I like hope, so here's to hoping for something awesome coming down the pipe for all of us!

IDC,

To be honest, i think high clock speeds were the focus all along, even in server SKUs. This is shown by the fact that they increased the pipeline substantially. Also, they moved from 3 AGU's to 2 AGU's, which corrected the memory storing problem by cutting input rather than increasing the ability to store. While theoretically this would result in the same throughput, in practice it would cut the throughput as there is no longer a ready instruction to store as there was in Stars. Although the memory subsystem is completely different in Bulldozer than Stars after the AGUs, so it is very difficult to compare the two in that way (in other words, take my assertion with a grain of salt).