But getting back to the noobish part, how can the logic shrink in area when the interconnects larger than the xtors? I suppose there's allot more 'empty' space at a microscopic level than I'm aware off, but that's all I've got.
Planar transistors are 2D animals, and those same 2 dimensions are in play with 2D finfets as well.
Now marketing likes to focus our attention on the sexiest dimension - the length of the transistor - because it is measured in tens of nanometers and everyone likes talking about how tiny their bits are
The xtor length is what is shown to you in all those sexy SEM/TEM images, the distance between the source and the drain, i.e. they show you the channel.
Now there is a good technical reason why engineers focus on the xtor length - this is the one that determines important parameters such as the switching speed.
But the other dimension, called the transistor width, is the one that doesn't get much attention in marketing but is the one that carries the bulk of the burden of shunting enough current across the channel to power the circuits at a given targeted clockspeed.
Idrive is reported in terms of a normalized parameter. Say 100 nA/um. The "per micron" is telling you the transistor width necessary to hit that 100nA value.
It is this transistor width that scales with Idrive. And this is true with FinFets as well.
So if GloFo increases the Idrive of their xtors with 14XM then it is very possible that chips designed for 20nm could experience a shrink in terms of not requiring the metal wiring to span as large of a transistor width as they need for the 20nm designs with its weaker transistors.