EETimes: ST plans for Dresden FDSOI production

[mrmt]

Ever heard of the "Not-invented-here" syndrome? They did not even list FD-SOI on their roadmap.

NIH would make sense for engineering folks working on GLF native process. Top executives whose bonus highly depends on the financial performance of the company wouldn't really mind whether FD-SOI was invented at GLF or not, they want profits, period.

You really would have to ask what the hell those guys were doing if they had a TSMC-killer process in their hands and didn't want to market it for the sake of their pride. I don't think even AMD management could be that amateurish and stupid.

 

[SocketF]

STM's PR blitz is as expected, they are trying to get top-dollar for their IP in licensing to GloFo. But GloFo is clearly not as convinced as STM that FD-SOI is all that STM touts it to be, otherwise GloFo would not be so conservative and guarded in their own commentary towards the technology.

Well if the selling company is hyping their product, trying to get a high price for their product, then it would only be logically that the buying entity will downplay the product, wouldn't it?

So far what we have with FD-SOI is a flurry of hype press releases

Don't forget, we also have already working silicon. Much more then some isotopes ^^

@mrmt:
The FD-SOI deal is probably not finished, and the executive's bonuses probably also depends on the price to pay to STM ...

 

[mrmt]

The FD-SOI deal is probably not finished, and the executive's bonuses probably also depends on the price to pay to STM ...

Every other relevant foundry out there is already committed to Finfet. Intel, UMC, TSMC, Samsung. IBM is an exception but won't license FD-SOI STM process, which leaves GLF as the sole possible customer for STM.

With such a TAM for their process STM has 0 leveraging margin in a negotiation. Yes, 0. Because GLF is already committed to finfets, it's just a matter of stick with the due course for them, they don't need SOI to execute their current business plan, which means they will adopt SOI only if they get very generous terms in the licensing agreement.

 

[SocketF]

IBM does not need to license FD-SOI from STM they are STM's research partner. FD-SOI is also used in IBM's research FAB in Albany.
(the flexible FD-SOI wafer I linked previously in this thread was produced there).

But they probably won't go into the foundry business and offer the process for anybody else ;-)

So I agree, GF is most probably the only option, but the more interest they can generate with their blitz-hype and their now demoed product the stronger their position in the negotiation with GF gets. Thus GF might be ill-adviced to foster that hype, too, if they are currently in price-talks. Let's see if GF's FDSOI opinion will have changed next year.

Apart from that:
There was also "fireside" chat at the Common Plattform meeting, there a eetimes journalist and Handel Jones from IBS (hp) chatted 30 min around everything, in the end he was asked about any risks/disruptors in the market in the future, and he said that mix-signal design is very though with finfets, thus he advices to have a "plan b" if things dont go that well with finfets. Besides using 28nm longer, he mentioned FD-SOI, because it "looks very positive", but I am not sure if Mr. Jones saw other PDFs than us, he only mentioned the usual stuff (easy reuse of bulk design, low power etc.)

P.S: To anybody who wants to see the slides in the common platform stream:
They removed the slides now. Thus you only see the presenter talking about some invisible slides ... very clever.

 

[mrmt]

So I agree, GF is most probably the only option, but the more interest they can generate with their blitz-hype and their now demoed product the stronger their position in the negotiation with GF gets. Thus GF might be ill-adviced to foster that hype, too, if they are currently in price-talks. Let's see if GF's FDSOI opinion will have changed next year.

I do not see how you can see strength in STM position with GLF, because there isn't any. STM cannot force GLF to adopt FDSOI, not even make GLF rush with a decision, because there is no other customer beyond GLF for their process and GLF doesn't need FDSOI to live, so the decision will be on GLF's terms and on GLF's time. What STM is trying to do by hyping FDSOI is attract prospective customers and buzz the press is to influence GLF analysis of the business. The sober GLF statements and the market bracket they are positioning FDSOI should say something about STM success in this.

 

[Khato]

Don't forget, we also have already working silicon. Much more then some isotopes ^^

Yes, they already have working silicon. And by their own presented figures it's not an awesome game-changer. The PR machine is careful to tout the possible speed increase without mention of how it affects power consumption, just as they are to tout power efficiency without the necessary context of what frequency such was achieved at. Sure it's better than 28nm bulk... but I'd expect that GloFo's "14XM" will be at worst equal in transistor characteristics while having the benefit of geometry scaling to reduce die size.

I somewhat wonder if the primary issue for the FD-SOI process now is one of simply being a bit too late to the party. What advantages exactly does it have over the upcoming/current finfet based processes? I know there's the 'ease' of design porting, but remind me how many products are currently shipping on GlobalFoundries' 28nm bulk process that could actually make use of this advantage? I don't believe that AMD's going to have a product using that process 'til the end of this year if they meet their roadmap. So if that advantage isn't in play, why would a customer design their product for the FD-SOI process instead of 20nm or 14XM where they get a smaller die size?

 

[SocketF]

I do not see how you can see strength in STM position with GLF, because there isn't any. STM cannot force GLF to adopt FDSOI, not even make GLF rush with a decision, because there is no other customer beyond GLF for their process and GLF doesn't need FDSOI to live, so the decision will be on GLF's terms and on GLF's time. What STM is trying to do by hyping FDSOI is attract prospective customers and buzz the press is to influence GLF analysis of the business. The sober GLF statements and the market bracket they are positioning FDSOI should say something about STM success in this.

Well GF needs to attract new customers. TSMC was reported lastly with having 100% market share of 28nm. Why should anybody else now switch to GF, if everything is nice there at TSMC? Why should you pay for additional investments to port a design to 28nm@GF? Of course nobody will do that. Therefore, if you are GF and cannot compete you have to differentiate and the best and cheapest option to do that is currently FD-SOI for GF. Most of the process is similar to 28nm, so no big investments are needed for GF, but the benefits for the customers are round about a full node shrink, hence GF could be competitive to TSMC's 20nm process with 28nm FD-SOI and attract new customers.

AMD currently does the same in their processor-market, they gave up on directly competing with intel and are looking for opportunities to differentiate themselves.

Yes, they already have working silicon. And by their own presented figures it's not an awesome game-changer. The PR machine is careful to tout the possible speed increase without mention of how it affects power consumption, just as they are to tout power efficiency without the necessary context of what frequency such was achieved at.

Back biasing allows you to raise the Vcore, and of course that will also raise your power consumption as any other jump in Vcore. Anybody who wants to raise Vcore and can live with the higher power consumption would be happy about it (e.g. FX-series customers). Depends all on the market segment.

Sure it's better than 28nm bulk... but I'd expect that GloFo's "14XM" will be at worst equal in transistor characteristics while having the benefit of geometry scaling to reduce die size.

You mean compared to 14nm FD-SOI? Or to 14nm FD-SOI with Finfets? The fun thing is, that you can combine both ;-)

I somewhat wonder if the primary issue for the FD-SOI process now is one of simply being a bit too late to the party. What advantages exactly does it have over the upcoming/current finfet based processes? I know there's the 'ease' of design porting, but remind me how many products are currently shipping on GlobalFoundries' 28nm bulk process that could actually make use of this advantage? I don't believe that AMD's going to have a product using that process 'til the end of this year if they meet their roadmap. So if that advantage isn't in play, why would a customer design their product for the FD-SOI process instead of 20nm or 14XM where they get a smaller die size?

a) The die size advantage is not that big as usual, bc 28nm FD-SOI is still on gatefirst, which saves some area compared to a gatelast process.

b) Ease of porting is no argument. As you said, there are no customers and I also wrote above that TSMC has 100% market share. The question is what you do next, after 28nm. Shrink to 20nm or port the design to 28nm FD-SOI?

As I wrote earlier in this thread the shrink to TSMC's 20nm won't give you as much performance/watt as usual. Then the process costs more and it also takes longer due to the needed double pattering (which also complicates the development process a bit). Compared to that, FD-SOI could give you a cheap way out. It has the same or better performance as a shrink to 20nm bulk@TSMC, the ability to choose between a high-performance&high-power or low-performance&very low-power mode, it's easier and faster to design, and has a shorter TimeToMarket, because you don't need double pattering.

Furthermore, GF is not capacity constraint, thus you will get your chips asap There are rumors that apple might order a lot from TSMC, soon, thus maybe smaller companies will be squeezed out.

 

[Idontcare]

GloFo still has opportunities with 28nm, be it FD-SOI or their standard HKMG bulk processes.

The TAM for 28nm will continue to grow for at least another 3 yrs as customers with cost-sensitive products currently fabbed on lagging edge nodes look to shrink them (without paying that bleeding-edge price premium) to 28nm in the years to come.

The difference is in the profits. By being late to the 28nm game they have left all the price premiums to TSMC, and TSMC is using those profits to invest back into developing nodes N+1 and N+2. Meanwhile the cycle of falling ever farther behind is continuing at GLoFo because their R&D efforts are being revenue-starved.

You need only look at any other foundry that has ever come (and nearly gone, like UMC and Chartered*) to see the cause-and-effect of sales revenue versus R&D and the feedback loop this creates in rendering the company uncompetitive in the future.

The IBM fab club was supposed to be AMD's (and then GloFo's) way out of this inevitable outcome, but the model is broken and it has to change. If it doesn't change then the fate is going to be indistinguishable from that had they never formed the fab club.

Consider, after all, the very reason why STM is trying to get FD-SOI installed at GloFo in the first place. STM has met the same fate that GloFo is trying to avoid - a cash-starved R&D engine that is failing to generate revenues necessary for securing a self-sufficient future.

STM can go fabless, as did AMD, but GloFo doesn't exactly have that option. They have no choice but to die trying.

* Chartered was good up through 65nm, then completely fell out of the running for 45nm and below, they'd be another SMIC at this point if it weren't for GloFo coming in and buying them up.

 

[Abwx]

STM can go fabless

They cant since they design , build and sell products that
have slim margins, with ferocious competition from Freescale ,
TI ,Renesas and thir likes.

Could TI become fabless and still survive ?.I doubt it.

 

[Khato]

Back biasing allows you to raise the Vcore, and of course that will also raise your power consumption as any other jump in Vcore. Anybody who wants to raise Vcore and can live with the higher power consumption would be happy about it (e.g. FX-series customers). Depends all on the market segment.

About the only market segment for forward body biasing I can see are overclockers - no one else is going to want to get anywhere close that portion of the power efficiency curve.

You mean compared to 14nm FD-SOI? Or to 14nm FD-SOI with Finfets? The fun thing is, that you can combine both ;-)

Sure about that? Or is that only wishful thinking? I mean, there might be a reason why STM's presentation materials lay out some information for 14nm and 10nm planar FD-SOI without a single mention of finfet. And I'm thinking it probably has something to do with the fact that Intel's 22nm materials state that the transistors are fully depleted by virtue of the finfet process. In that case, would there be any advantage to combining it with FD-SOI? I'm not aware of any.

As well, I was comparing the 28nm FD-SOI that STM is pushing against the 14XM process that GlobalFoundries is promising for next year, or at least their 20nm process that'll supposedly be available this year. Why? Because 'risk production' for 28nm FD-SOI is Q4 of 2013 according to the recent statements... and according to the 14XM FAQ on GlobalFoundries' website they were expecting to deliver 20nm silicon to customers in 2H of 2012 and have customer tape outs of 14XM in 2013. So supposedly their 20nm process will be available before 28nm FD-SOI, and 14XM will be available shortly after...

a) The die size advantage is not that big as usual, bc 28nm FD-SOI is still on gatefirst, which saves some area compared to a gatelast process.

Oh? I take it you've seen details on GlobalFoundries' 20nm and 14XM processes then? Or is this simply a guess based only on the general difference between gate first/gate last areas? Because even if that does hold true there's still a pretty marked savings in die size going from 28nm to 20nm.

b) Ease of porting is no argument. As you said, there are no customers and I also wrote above that TSMC has 100% market share. The question is what you do next, after 28nm. Shrink to 20nm or port the design to 28nm FD-SOI?

As I wrote earlier in this thread the shrink to TSMC's 20nm won't give you as much performance/watt as usual. Then the process costs more and it also takes longer due to the needed double pattering (which also complicates the development process a bit). Compared to that, FD-SOI could give you a cheap way out. It has the same or better performance as a shrink to 20nm bulk@TSMC, the ability to choose between a high-performance&high-power or low-performance&very low-power mode, it's easier and faster to design, and has a shorter TimeToMarket, because you don't need double pattering.

Yeah, if you assume that shrinking to 20nm and porting from any other 28nm foundry to 28nm FD-SOI are roughly equal in terms of design work, which seems reasonable, then it's just a question of how 20nm bulk compares to 28nm FD-SOI. Sadly I've not found any technical information for TSMC's 20nm bulk floating around from IEDM 2012. But even if it's slightly worse than 28nm FD-SOI the increased cost per wafer will still be more than offset by decreased die size, so it's not exactly a clear decision.

 

[Idontcare]

They cant since they design , build and sell products that
have slim margins, with ferocious competition from Freescale ,
TI ,Renesas and thir likes.

Could TI become fabless and still survive ?.I doubt it.

Uh...TI did go fabless for 45nm and beyond. Remember, I was there when it happened, and I'm no longer there because it happened

TI kept their 65nm and older fabs to continue running existing product, but everything newer has been done at the foundries. They also intend to continue manufacturing analog chips in house, but that is all at 180nm and 130nm.

All those companies you list have either gone fabless or are in the process of going fabless because they can't justify the process node R&D nor the capex required to maintain a competive leading edge. It stopped being critically enabling right around the 65nm node.

 

[Abwx]

It may be true for leading hedge processes but most of theses
firms products are not using such nodes when it is not just
discrete components for automotive and consumer applications.

For instance STMicro produce a lot of transistors whose replacement
by indian or chineses factories are just complete failure , or just look
at TI buyout of Burr Brown (and NS) for the analog portfoglio.

 

[mrmt]

Well GF needs to attract new customers. TSMC was reported lastly with having 100% market share of 28nm. Why should anybody else now switch to GF, if everything is nice there at TSMC?

Exactly, nobody would. The customers who are already with TSMC 28nm are almost 1st tier customers that won't switch to 28nm at GLF, SOI or not SOI, because they are all gearing up to 20nm in TSMC. GLF is trying to get customers who hadn't committed to TSMC 28nm, which are most LP/SLP 2nd tier customers.

 

[SocketF]

Consider, after all, the very reason why STM is trying to get FD-SOI installed at GloFo in the first place. STM has met the same fate that GloFo is trying to avoid - a cash-starved R&D engine that is failing to generate revenues necessary for securing a self-sufficient future.

Hmm after 28nm yes, but currently they have 28nm more ready in their own fab in Crolles. Not sure why they want now GF, too, I guess Crolles is rather a small fab with low volumn and/or they want GF to get some experience with FD-SOI, they'll need them later for 14nm anyways ;-)

Thanks for all the other (here unquoted) insights, really interesting to read.

About the only market segment for forward body biasing I can see are overclockers - no one else is going to want to get anywhere close that portion of the power efficiency curve.

Well check the current CPU-products with >40W TDP. That is basically the market for that. A "bit" broader then mere overclockers ;-) FD-SOI furthermore saves some power due to lower leakage due to the roots in the LP-libraries, thus it should be quite competitive in terms of performance/watt.

Sure about that? Or is that only wishful thinking?

Yes sure, one link of many:
http://www.advancedsubstratenews.co...l-positioned-to-deliver-optimal-finfet-value/

I mean, there might be a reason why STM's presentation materials lay out some information for 14nm and 10nm planar FD-SOI without a single mention of finfet.

Well finfets are IBM's research, STM is not doing it. But it is on the roadmap (3D-FD):

IBM will use SOI-Finfets@14nm for their high-performance process, they mentioned it as successor of their last SHP 22nm PD-SOI process.
Companies can choose, if they are shy of the extra costs of 3D, then they can stick to 2D until 10nm.

And I'm thinking it probably has something to do with the fact that Intel's 22nm materials state that the transistors are fully depleted by virtue of the finfet process. In that case, would there be any advantage to combining it with FD-SOI? I'm not aware of any.

Yes, process costs. The Soiconsortium mentioned 7 Litho and 56 process-steps for Fins@SOI, on bulk these are 9 and 91(!). The Soi wafer is more expensive yes, but the faster Fab-time and better yields are then in total pro SOI - at least according to the SOI people ... probably biased, but I don't think that the basic information about the process steps are wrong.

As well, I was comparing the 28nm FD-SOI that STM is pushing against the 14XM process that GlobalFoundries is promising for next year, or at least their 20nm process that'll supposedly be available this year. Why? Because 'risk production' for 28nm FD-SOI is Q4 of 2013 according to the recent statements... and according to the 14XM FAQ on GlobalFoundries' website they were expecting to deliver 20nm silicon to customers in 2H of 2012 and have customer tape outs of 14XM in 2013. So supposedly their 20nm process will be available before 28nm FD-SOI, and 14XM will be available shortly after...

Well if it is 28nm FD-SOi against 14XM then the latter will probably better, but I wont believe GF's promises on their delivery times. As IDC wrote previously, GF is rushing too much too soon. 28nm was terribly late, according to old promises they were ready with 28nm in the end of 2010(!). Double pattering @20nm and finfets@14nm now doesn't make the process easier. Hopefully, GF will surprise as all and deliver what they promise, but I have my doubts.

Oh? I take it you've seen details on GlobalFoundries' 20nm and 14XM processes then? Or is this simply a guess based only on the general difference between gate first/gate last areas? Because even if that does hold true there's still a pretty marked savings in die size going from 28nm to 20nm.

Only a guess, bc 20nm is gate last for sure. Yes, of course you are correct, the absolut difference is still not that small, but as I said it will be smaller than usual. GF said gate-last will save 10%-20%,a full node shrink saves ~30% (factor 1,41 smaller), thus in the end you roughly gain only 10-20%, theoretical. I guess in practice the metal pitch is very important, too. No clue what numbers we are talking about then, if it is GF@28nm vs. TSMC@20nm.

Yeah, if you assume that shrinking to 20nm and porting from any other 28nm foundry to 28nm FD-SOI are roughly equal in terms of design work, which seems reasonable, then it's just a question of how 20nm bulk compares to 28nm FD-SOI. Sadly I've not found any technical information for TSMC's 20nm bulk floating around from IEDM 2012. But even if it's slightly worse than 28nm FD-SOI the increased cost per wafer will still be more than offset by decreased die size, so it's not exactly a clear decision.

Well yes it's a complicated calculation, first the die-size advantage is important, but we cannot be sure and then you also have to think about yields. These will be worse for 20nm in the beginning, so in the end you might get more good dies out of a 28nm wafer.

 

[SocketF]

Exactly, nobody would. The customers who are already with TSMC 28nm are almost 1st tier customers that won't switch to 28nm at GLF, SOI or not SOI, because they are all gearing up to 20nm in TSMC. GLF is trying to get customers who hadn't committed to TSMC 28nm, which are most LP/SLP 2nd tier customers.

Hmm I thought about it again, you are probably right here, but given GF's better yields at 28nm now and e.g. nVidias complaint about raising fabbing-costs, FD-SOI could be a not that bad option for e.g. a mobile GPU. I don't think that 20nm @TSMC could beat 0.6V@1GHz. Combined with a possible cheaper manufacturing (I assume 28nm FD-SOI is cheaper than 20nm bulk, not sure if this will be correct) it could be an interesting option.

If apple will buy most of TSMC's capacity, then even more.

But well, 28nm FD-SOI it's not 100% the same as the current 28nm bulk stuff, who knows if GF will have problems again, even if it is the same node

 

[mrmt]

Hmm I thought about it again, you are probably right here, but given GF's better yields at 28nm now and e.g. nVidias complaint about raising fabbing-costs, FD-SOI could be a not that bad option for e.g. a mobile GPU. I don't think that 20nm @TSMC could beat 0.6V@1GHz. Combined with a possible cheaper manufacturing (I assume 28nm FD-SOI is cheaper than 20nm bulk, not sure if this will be correct) it could be an interesting option.

28nm FDSOI is too late to the party. Not only it missed the 28nm bandwagon 2 years go, designs for TSMC 20nm should be well on its way. Nobody will scrap their 20nm designs in order to move down to 28nm FDSOI, better to wait for TSMC to build 20nm capacity than scrap the design and give GLF - a foundry without credibility - a chance with an unproven manufacturing technology.

GLF focus on LP/SLP customers is not a SOI limitation, but a recognition of this fact. The TAM for 28nm FDSOI is not the first tier customers, but the 2nd and 3rd tiers MPU companies that are stuck with 40nm and 65nm nodes and, as a bonus, are a lot more resilient to delays/snafus in HVM.

 

[SocketF]

Ah right, forgot the design overhead. You are right, everybody is probably already working @20nm stuff.

 

[Abwx]

Including Glofo NY....

Technology development is well underway and our Fab 8 in New York began running full-loop 20nm silicon in January. We have multiple active customer design activities with silicon delivery expected by 2H 2012.

From the link above.

Anyway , that seems to be for low power designs pnly.

 

[Ajay]

Including Glofo NY....

From the link above.

Anyway , that seems to be for low power designs pnly.

So, where is AMD going to get 28nm SHP for Kaveri? And does big core die, no SHP for the next Opterons in 2014?

And what's with GF doing 14 XM? No second source opportunities from TSMC customers. What is GF business plan?

Lastly, I read 14 XM's smallest metal layer will be the same as the 20nm, so this sounds like no die shrink, so lower power but no more dice per wafer an no cost benefit for customers.

Seems just bizarre to me.

 

[mrmt]

So, where is AMD going to get 28nm SHP for Kaveri? And does big core die, no SHP for the next Opterons in 2014?

If you look for old roadmaps you'll find buried a 28nm SHP process in 2013 and a 20nm SHP process for 2014. As of now they are not something GLF is actively marketing, they are all about their LP/SLP processes.

 

[SocketF]

Lastly, I read 14 XM's smallest metal layer will be the same as the 20nm, so this sounds like no die shrink, so lower power but no more dice per wafer an no cost benefit for customers.

Well yes, no die-shrink, but as long as you dont need more pin-contacts you can use more transistors on the chip. So it is not that bad - if I understand it correctly

Seems just bizarre to me.

Yes, but they want to save some time to be able to catch up with intel. Not sure if they'll manage it though.

@mrmt:

28SHP just re-appeared at the common platform summit some days ago:

http://www.eetimes.com/electronics-...ce-to-14-nm-as-IBM-waits-for-EUV?pageNumber=2

:ninja:

But 20nm SHP is gone for sure it seems.

 

[Idontcare]

Well yes, no die-shrink, but as long as you dont need more pin-contacts you can use more transistors on the chip. So it is not that bad - if I understand it correctly

If the drive currents are higher with 14XM vs 20nm then there is opportunity to shrink the die because you won't need as wide of transistors at 14XM as you do at 20nm. Your sram won't get smaller but circuits can.

 

[ShintaiDK]

It is a pretty big PR gimmick tho to call 14XM for 14. Since they use 20nm interconnects.

 

[Idontcare]

It is a pretty big PR gimmick tho to call 14XM for 14. Since they use 20nm interconnects.

No question there.

But <prepare thyself for imminent mandatory insertion of car analogy in 3...2...1>...Mazda had their 2014 Mazda 6 sedan available for review on showroom floors (and in production for Jan 2013 sales) in Oct 2012 :hmm:

Now most people would look at that and say to themselves "damn, so Mazda totally blew their timeline for getting their 2012 Mazda 6 sedan to market in 2012, so they pushed it back a year, launched it in October, and relabeled it the '2014 model' as if it were somehow nearly 2yrs ahead of its time and schedule...right".

But not in the lalaland of marketing where you can buy yourself "2014" cars in Jan 2013 that was manufactured in 2012, and get yourself some 14XM transistors manufactured on a 20nm node.

Its all marketing which is why none of it matters. What matters is the performance, when it is actually available and what does it do for you and your dollars.

That isn't to say there is no truth in marketing, but you have to know what you are doing (in a technical professional sense) to know which parts of the marketing are based on fact versus those which are based on fiction.

That is where the novices and amateurs really make themselves self-evident because they seize on the silliest of marketing talking points as if they were fact, and fail to recognize the obvious realities that are being betrayed by the marketing when the truth is right there hidden in plain site on the slide. (that sounds far more snobbish than intended but I don't really know how else to write it)

The part to never lose sight of is that absolutely none of the talk matters, be it talk by marketing folks or talk in forums by folks who aren't educated/experienced enough to know the difference...all that matters is the product (if and when it arrives) and performance (power, expense, performance, etc).

 

[Ajay]

Well, by now I think we've all seen the TEM crossections of xtors and know that the marketing claims are just that (I don't think I could work in marketing, I'd have to shoot someone [I'm not suicidal :|]). But getting back to the noobish part, how can the logic shrink in area when the interconnects larger than the xtors? I suppose there's allot more 'empty' space at a microscopic level than I'm aware off, but that's all I've got.

By the way, thanks for all the answers guys.