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Does an 8/8 Zen "Summit Ridge" SKU make good sense?

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Does an 8/8 Zen "Summit Ridge" SKU make good sense?


  • Total voters
    52
  • Poll closed .

Valantar

Golden Member
Aug 26, 2014
1,792
508
136
Let's see how this "worse performance" looks like depending on CPU load, considering SMT would account for about +25% IPC increase and taking 6c/6t as the base for relative performance increase:
  • Until 6 threads both 8c/8t and 6c/12t will perform at almost identical performance levels with a 6c/6t, including power usage.
  • At 7 threads the 8c/8t will offer 16% more performance and the 6c/12t will bring +4% over 6c/6t.
  • At 8 threads the 8c/8t will be at +33% , the 6c/12t will offer +8%.
  • At 10 threads the 6c/12t will jump at 16% relative advantage, still considerably behind the 33% advantage of the "inferior" 8c/8t.
  • It takes 12 threads for the 6c/12t to hit it's max throughtput of +25%, and with the help of somewhat smaller power usage at full load come out even or slightly on top of the 8c/8t.
While some may argue SMT offers a bit more power efficiency than extra raw cores - leading to higher clocks , this will only happen in scenarios where thread count well past 8, more likely 10-12.

Moral of the story? SMT needs higher thread count to truly shine. Physical cores kick in faster.
You're not factoring in that a 6/12 SKU will undoubtedly be clocked higher than an 8/8 SKU, which should easily make up for any performance deficit in the "virtual" threads. This is especially important as most workloads today outside of video rendering or other very parallel workloads have varying performance requirements per thread (and mostly require 1-2 high performance threads and a bunch of low-to-mid priority background tasks., and ultimately, single thread performance is still the most important. If a 6/12 SKU is clocked 2-300 MHz higher than an 8/8 SKU (which, given the same TDP, seems likely), it would be better for the vast majority of consumer workloads.

Ask Intel, they've been doing this kind of wasting for many years now.
No they haven't. Where are the HEDT i5s, if I might ask? They don't exist, as they have long since realized that at high core counts, non-SMT SKUs make little to no sense.

If that were true, then consumer would have nothing to gain from a 6c/12t chip either. Everything above 4c/8t simply doesn't make any sense, high clocked Intel 4/8 chips also beat lower clocked 6/12 chips.
Here you're partially right. I see 6/12 as a good compromise - 4/8 will undoubtedly win in therms of ST performance, but as games and applications grow ever more parallel, two more physical cores (and four more threads) will become increasingly more important. And compared to 8/8 or 8/16, the clock deficit compared to 4/8 wouldn't be nearly as large for 6/12. Intel's HEDT line show this pretty clearly - when moving from 6 to 8 cores you only lose 100MHz max boost, but a whopping 400MHz in base clocks (which do matter more in high usage scenarios). This is clearly to conserve power/lower heat output.
Well, yeah. The point of it is to maximize AMD's revenue.
How would this maximize their revenue? You realise that an 8/8 SKU would require them to take fully functional chips, disable SMT, and sell them at a lower price, right?
 

AtenRa

Lifer
Feb 2, 2009
13,554
2,536
126
You're not factoring in that a 6/12 SKU will undoubtedly be clocked higher than an 8/8 SKU, which should easily make up for any performance deficit in the "virtual" threads.
FX 8350 = 4M 8T at 4GHz base, 4.2GHz turbo - 125W TDP
FX 6350 = 3M 6T at 3.9GHz base, 4.2GHz turbo - 125W TDP

AMD could do the same with ZEN 8C and 6C SKUs
 

Valantar

Golden Member
Aug 26, 2014
1,792
508
136
FX 8350 = 4M 8T at 4GHz base, 4.2GHz turbo - 125W TDP
FX 6350 = 3M 6T at 3.9GHz base, 4.2GHz turbo - 125W TDP

AMD could do the same with ZEN 8C and 6C SKUs
Yep, they could. If Zen turns out to be as much of a dud as all the heavy machinery. Also, I'd like to see real-world power consumption numbers for those parts. Either the 6350 is bottom-of-the-barrel power binning, or AMD really, really wanted people to buy their 8c parts. (Which we know they do, as they're the only semi-competitive parts in the FX lineup after all.)
 

coercitiv

Diamond Member
Jan 24, 2014
4,166
5,069
136
You're not factoring in that a 6/12 SKU will undoubtedly be clocked higher than an 8/8 SKU, which should easily make up for any performance deficit in the "virtual" threads. If a 6/12 SKU is clocked 2-300 MHz higher than an 8/8 SKU (which, given the same TDP, seems likely), it would be better for the vast majority of consumer workloads.
Please give details on how 6/12 chips will clock 2-300Mhz higher than 8/8 in both low threaded and highly threaded scenarios.

Let's say 6/12 gets a 10% frequency advantage and redo perf bonus over 6/6 in a 10 threaded game:
6/12 @ 110% frequency will be 27% faster than 6/6 @ 100% frequency
8/8 @ 100% frequency will be 33% faster than 6/6 @ 100% frequency

Again, even with 10% increased clocks you still need 11+ threads to come out on top.

This is especially important as most workloads today outside of video rendering or other very parallel workloads have varying performance requirements per thread (and mostly require 1-2 high performance threads and a bunch of low-to-mid priority background tasks., and ultimately, single thread performance is still the most important.
You just blew up your own argument: if most workloads require 1/2 high perf threads and some low/mid priority threads, then adding SMT into the mix may end up clearly hurting ST performance in some applications. The 8/8 chip will never suffer from such problems, always offering maximum ST performance arch can achieve.

Moreover, since many threads will not stress the cores to their maximum, even the 8/8 chip will clock higher towards arch fmax - considering turbo clocks will be relative to power usage.

SMT is a boon for extracting every last drop of performance out of a fixed size area of silicon. That does not make it inherently better than using more silicon area to increase throughput, especially if ST performance is still a factor and number of threads may vary, not necessarily reaching the number needed for efficient SMT usage.

Later edit: when giving examples of power usage from the Intel HEDT line to show frequency drop from 8c to 4c, please keep in mind HEDT chips have a different uncore than mainstream chips.
 
Last edited:

Valantar

Golden Member
Aug 26, 2014
1,792
508
136
Please give details on how 6/12 chips will clock 2-300Mhz higher than 8/8 in both low threaded and highly threaded scenarios.

Let's say 6/12 gets a 10% frequency advantage and redo perf bonus over 6/6 in a 10 threaded game:
6/12 @ 110% frequency will be 27% faster than 6/6 @ 100% frequency
8/8 @ 100% frequency will be 33% faster than 6/6 @ 100% frequency

Again, even with 10% increased clocks you still need 11+ threads to come out on top.


You just blew up your own argument: if most workloads require 1/2 high perf threads and some low/mid priority threads, then adding SMT into the mix may end up clearly hurting ST performance in some applications. The 8/8 chip will never suffer from such problems, always offering maximum ST performance arch can achieve.

Moreover, since many threads will not stress the cores to their maximum, even the 8/8 chip will clock higher towards arch fmax - considering turbo clocks will be relative to power usage.

SMT is a boon for extracting every last drop of performance out of a fixed size area of silicon. That does not make it inherently better than using more silicon area to increase throughput, especially if ST performance is still a factor and number of threads may vary, not necessarily reaching the number needed for efficient SMT usage.

Later edit: when giving examples of power usage from the Intel HEDT line to show frequency drop from 8c to 4c, please keep in mind HEDT chips have a different uncore than mainstream chips.
Of course all of this is suppositions and guesstimation, but from looking at other CPUs and their TDPs and power consumption, assuming a ~10% increase in max clocks for a 25% decrease in cores (even with SMT added in) seems reasonable to me. Of course, I might be wrong here. As might you. We'll see in January, I suppose. It's entirely possible that AMD will want to push users towards 8c parts by clocking 6c parts lower.

Also, your scenario of turbo usage assumes ideal and fully functional dynamic per-core turbo. Not even Intel has this, and they really focused on that for Kaby Lake. Now, we don't know anything at all about how Zen will turbo. Whatsoever. But I prefer taking a cautious approach, so I assume max turbo is for 1-2 cores max, with tiered turbo levels for more cores under full load. And as no cores without OC'ing will exceed the max turbo spec, a lower core count part with more thermal headroom should turbo higher. It's also reasonable to assume this carries down the line for multi-core turbo - i.e. if a 6-core part turbos to 4,2 with 2 cores active, and an 8-core to 4,0, then I'd assume a similar drop in frequency for both when adding more cores. I.e. the clock difference would stay for however many cores are under load.

Which means this:
-a 6/12 part would have more cores/threads to offload background tasks off of any requiring high performance
-a 6/12 part would consistently perform ~10% better in ST tasks
-a 6/12 part would perform better than an 8/8 part for MT tasks up to 6 threads (given that background tasks could be handled by 6 "simultaneous" threads)

Not to mention that a 25% reduction in active cores should be good for overclocking headroom.

The only situation in which an 8/8 part would perform better would be in heavy 7-8 thread workloads - which are exceedingly rare.
 

coercitiv

Diamond Member
Jan 24, 2014
4,166
5,069
136
Of course, I might be wrong here. As might you. We'll see in January, I suppose.
I think we can safely agree we are both making a number of assumptions here. I think it will be very interesting to see how this turns out, especially if we end up with both SKUs on the market and we get to compare theories. I mean that in the most friendly way, for me it's fun to estimate this kind of things, even in the event of being wrong.

Also, your scenario of turbo usage assumes ideal and fully functional dynamic per-core turbo.
My scenario assumes all core turbo speed will be chosen relative to overall power consumption, not thread usage. It does not require independent per-core turbo. Intel has this, and has been perfecting this for years now. All cores turbo together as high as possible as long as power threshold is not reached. AMD also has something similar, developed during their XV mobile efforts. Proper power management is a must for them, it could essentially fail Zen launch.

Now, we don't know anything at all about how Zen will turbo. Whatsoever. But I prefer taking a cautious approach, so I assume max turbo is for 1-2 cores max, with tiered turbo levels for more cores under full load. And as no cores without OC'ing will exceed the max turbo spec, a lower core count part with more thermal headroom should turbo higher.
So, we don't know anything about turbo mechanism, and not knowing enables us to presume 6/12 will clock decisively higher than 8/8. I think we can do better than that: let's see how SMT + 10% increased clocks works out for Intel in terms of power usage.



This is a power delta graph published by Anandtech in their Skylake review. Granted power delta figures are not advised when trying to do accurate calculations, but for the purpose of this napkin math they are good enough (we're interested in relative power usage, not absolute values). In fact, in order to make sure the 6700K power usage was not badly influenced by some bad settings, I will consider a more simplified and clearly more SMT advantageous data set of 60W for 6600K and only 90W for 6700K.

So, when adding SMT + 10% frequency increase, mainstream Skylake chips can consume 50% more power. SMT is not free, and 10% increased frequency towards the upper frequency spectrum is definitely expensive. By contrast going from 6 to 8 cores is a 33% increase.
 

Valantar

Golden Member
Aug 26, 2014
1,792
508
136


This is a power delta graph published by Anandtech in their Skylake review. Granted power delta figures are not advised when trying to do accurate calculations, but for the purpose of this napkin math they are good enough (we're interested in relative power usage, not absolute values). In fact, in order to make sure the 6700K power usage was not badly influenced by some bad settings, I will consider a more simplified and clearly more SMT advantageous data set of 60W for 6600K and only 90W for 6700K.

So, when adding SMT + 10% frequency increase, mainstream Skylake chips can consume 50% more power. SMT is not free, and 10% increased frequency towards the upper frequency spectrum is definitely expensive. By contrast going from 6 to 8 cores is a 33% increase.
You're correct about this, but this is under a power virus type load that maxes out every core constantly - not exactly something that happens in real life. And it's logical - the point of SMT is to better utilize unused silicon by running different calculations simultaneously. As such, "ideal" SMT would essentially double per-core power consumption, given 100% better silicon utilization. That's a given. But if, as you say, turbo speed is regulated by power rather than activity, this would still IMO favour the 6-core part given that it has less actual silicon to utilize. After all, unless the SMT threads are under heavy load, they don't use noticeable power, and stacking background processes onto unused physical cores that are then not-quite-idle, rather than executing them simultaneously on an already in-use core at least sounds less efficient to me. That Intel consistently pushes SMT on mobile in low-power scenarios corroborates this, at least in my mind. If non-SMT was potentially more efficient for the same workload, we'd se far more 4C4T mobile CPUs out there.
 

arandomguy

Senior member
Sep 3, 2013
531
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116
That Intel consistently pushes SMT on mobile in low-power scenarios corroborates this, at least in my mind. If non-SMT was potentially more efficient for the same workload, we'd se far more 4C4T mobile CPUs out there.
I don't know if that is a good line of reasoning.

Intel also pushed a non-SMT arch for even more power constrained segments with Atom.

Are there SMT ARM mobile CPUs?
 

EightySix Four

Diamond Member
Jul 17, 2004
5,115
49
91
I don't know if that is a good line of reasoning.

Intel also pushed a non-SMT arch for even more power constrained segments with Atom.

Are there SMT ARM mobile CPUs?
Doesn't Intel do four threads per core on Phi?

Other than Apple's chips, are any of the mobile CPUs wide enough to benefit from SMT?
 

coercitiv

Diamond Member
Jan 24, 2014
4,166
5,069
136
But if, as you say, turbo speed is regulated by power rather than activity, this would still IMO favour the 6-core part given that it has less actual silicon to utilize.
The 6/12 would indeed have an inherent advantage over the 8/8, and here I can offer some of my own data collected to better understand how desktop Skylake chip behaves from a power usage perspective. The following table represents idle power usage for a 4/4 Skylake core. The numbers are slightly inflated because of a voltage bump my BIOS played on me, but they are nevertheless good enough to illustrate the situation (true "stock" voltage interval should be 0.81-1.15V).



Judging by this table, 2 Skylake cores sitting idle @ 4Ghz use around 3-4W while under 30C, so in in a hypothetical "warm" mainstream 8/8 Skylake CPU that would incur a 5-6W penalty (we consider the rest of them are doing real work and the chip goes turbo all the way up, so high frequency and high temps). Add some kind of light load and the penalty will increase, but then again once you put any real load on them it's hard to estimate when that load becomes lucrative, turning penalty into bonus.

Under some loads the 6/12 chip might end up with something like 6-10W of extra headroom, but then again this headroom will matter only as long as the 8/8 chip will have reached it's TDP limit. It seems to me the 6/12 chip might have the upper hand at 4-6 threads, loose between 7-10, then come back at 11-12 for a tie. Between 1-3 threads power usage should not affect max clocks.

After all, unless the SMT threads are under heavy load, they don't use noticeable power, and stacking background processes onto unused physical cores that are then not-quite-idle, rather than executing them simultaneously on an already in-use core at least sounds less efficient to me. That Intel consistently pushes SMT on mobile in low-power scenarios corroborates this, at least in my mind. If non-SMT was potentially more efficient for the same workload, we'd se far more 4C4T mobile CPUs out there.
It would be naive of me to come up with such an idea - that in general SMT is less efficient than adding cores. The cost alone of increasing chip area makes SMT a no brainer, but this is a unique situation where the chip maker creates the new chip by slashing features in the most advantageous way - a blend of cost optimization and fighting the competition.

In my view the 6/12 and 8/8, although offering different performance profiles, are too close in the end to warrant both SKUs, unless one of them is crippled in some way (binning, cache etc). However, it is my opinion that 8/8 would be more competitive against the 4/8 chip of the competition, which will have far better ST perf due to a combination of better IPC and higher clocks, but will start loosing steam after 4 threads and eventually tie towards 7 threads. (i made another post on the matter on the Zen thread if you care to know my reasoning).

I should mention one more thing which I implied but never stated: my entire theory on 6/12 vs. 8/8 is based on the assumption that Zen, in it's first iteration, will have trouble efficiently clocking past 4Ghz. If this is not the case, and going past 4Ghz is not met with sharp power increase, then 6/12 will indeed have more wiggle room frequency wise, likely making it a better candidate than 8/8.
 

sirmo

Golden Member
Oct 10, 2011
1,011
374
136
Segmentation. It makes sense if they can charge a higher premium for the 8/16. The people who need 16 threads are also a different market, often enough, to justify 8/16 and 8/8, I assume.
Segmentation makes no sense for AMD.. unless we're talking binning to improve yields. They are not trying to protect high end products from being cannibalized.. they are facing an Intel monopoly. I highly doubt AMD would disable features, other than OC unlock for binned high end parts.

For instance Nvidia disables SLI on 1060, AMD doesn't disable crossfire on any of their GPUs. Nvidia does it to protect it's 1070 and 1080 from being cannibalized by their own products.

I am pretty sure you'll be able to disable "hyperthreading" if you don't want to use it.
 

LTC8K6

Lifer
Mar 10, 2004
28,523
1,570
126
Segmentation makes no sense for AMD.. unless we're talking binning to improve yields. They are not trying to protect high end products from being cannibalized.. they are facing an Intel monopoly. I highly doubt AMD would disable features, other than OC unlock for binned high end parts.

For instance Nvidia disables SLI on 1060, AMD doesn't disable crossfire on any of their GPUs. Nvidia does it to protect it's 1070 and 1080 from being cannibalized by their own products.

I am pretty sure you'll be able to disable "hyperthreading" if you don't want to use it.
I think AMD needs to keep this simple.

Offer more threads at reasonable clocks and reasonable ipc at a reasonable price.

That's all they need to do.

They don't need to get fancy or complicated.
 
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superstition

Platinum Member
Feb 2, 2008
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FX 8350 = 4M 8T at 4GHz base, 4.2GHz turbo - 125W TDP
FX 6350 = 3M 6T at 3.9GHz base, 4.2GHz turbo - 125W TDP

AMD could do the same with ZEN 8C and 6C SKUs
A few relevant quotes:
The Stilt said:
I don't think the actual TDP is the main reason for the low clocks. A vast majority of the potential Zeppelin purchasers would still buy it despite the higher (e.g 125W) TDP, if there was large performance improvement over a 95W TDP model. I think the reason for sticking with the original 95W TDP is that beyond that point the process operates so far beyond it's ideal range, that the actual frequency improvements from the increased power budget are negligible. This brings us back to Polaris 10 (same most likely applies on P11) where the effect can be seen starting from the 1GHz / 860mV mark. I'm pretty certain AMD didn't originally plan to run Polaris at the clocks and voltages they ended up releasing them at (up to 1266MHz / 1.15V). Most likely the launch of Pascals took them by complete surprise and were forced to react in the only way they at that point could.
The Stilt said:
95W TDP Zeppelin parts should draw around ~ 80W from the primary (VDDC, CPU core) power plane. The rest (~15W) is for the northbridge, IO, FCH, etc and will be drawn from the secondary VDD_SoC plane and other minor, low-current planes.
The Stilt said:
Single core turbo @ 3.5GHz might be possible if the process improves enough, but there is no power budget available for 3.5GHz base even if it was otherwise possible. Remember that the CCXs alone do not have the full power budget in their disposal. On 95W TDP parts I would expect that the NB and the FCH consume at least 15W combined.
The Stilt said:
To me the 95W 4C/8T appears to be pretty unlikely, since the Fmax appears to be fully limited by the manufacturing process itself and not by the power limit (based on the alleged extremely tiny delta between the base clock and max turbo). So increasing the TDP from 65W to 95W would basically make no difference in the clocks or the performance.
The Stilt said:
The Fmax vs. Vdd curve on 14nm LPP is vastly steeper than on 28nm HPP, close and beyond the optimal Fmax range. 14nm LPP is superior to 28nm HPP when it operates at it's optimal range, but anything outside this range is far inferior.
If everything he said is accurate it does seem to make more sense to have 125W parts. This would compensate for the higher power draw due to the clocks being outside of the optimal range for 14nm LPP and for the NB/FCH draw.

Why isn't AMD offering 125W parts, allegedly? It could be to please board makers who don't want to spend to make the boards quality enough:

The Stilt said:
When AMD moved from 32nm SHP SOI to 28nm BULK the voltage stability became extremely important. Despite the platforms using parts made with different processes (e.g AM3+ and FM2+) had exactly the same load-line specification (1.3mOhms) in reality the smaller and othewise inferior 28nm process was significantly more sensitive to voltage variations / fluctuations. Achieving a stable voltage supply through proper (load dependent) load-line calibration can result in hundreds of MHz additional headroom when close to Fmax, even on the more recent 28nm (Godavari) chips.

For Zen the load-line appears to be (based on the existing VRM designs) significantly tighter than it was with previous AMD designs and much tighter than the Intel VR12 spec (which is already strict) specifies...
The Stilt said:
Three major manufacturers (ASRock, MSI and Gigabyte) are selling 125W and 220W "compatible" motherboards, which in reality cannot reliabily (without protections kicking in, at stock) support even the 125W rated parts in conditions which are better than the infrastructure specifications require. ASRock is the worst violator by a landslide and they still claim that their 970 Performance and 990FX Extreme6 motherboards equipped with a fake (no hardware for doubling), analog "8+2 phase" VRM support 220W TDP parts. People have been complaining about throttling issues on these boards even on stock 125W parts, since the day they were released.

The PCB on ASRocks is in it's own class, because it is literally paper thin. I accidentally bent the board so much that some of the SMD components popped of, just by lifting the board out of the box. These issues are unfortunately not limited to just ASRock, the lower-end motherboards from every single manufacturer is affected.
The Stilt said:
For a 8C/16T Zeppelin I wouldn't even consider a motherboard with a 4+2 phase config. While a making a board with sufficient 4+2 phase VRM is entirely possible (as previously said), none of the manufacturers will use high enough quality components in their boards to make a 4+2 phase configuration good enough. A native 6+2 phase configuration will be used on the high quality mainstream / high-end boards. There will most definitely be doubled (4+1 to 8+2, etc) solutions too, especially in the cheaper "enthusiast" / "high-end" boards.

The VRM requirements on Zeppelin & Raven are not demanding due the high power draw, but due the high current draw.
The Stilt said:
The load-line specification for both AM3+ and FM2+ is extremely loose (1.3 mOhm & 2.1mOhm) and because of that the voltage droop by the specification is very large. To ensure that the operation parameters remain within a spec, an AM3+ part which draws 100A of current and requires 1.3000V to be fully stable must have at least 1.4300V default voltage (130mV droop @ 100A). Some of the motherboards are built to have lower Rll (< 1.3mOhm / 2.1mOhm) than the specification dictates, or the end-user might adjust it to be lower than the default value. If the droop is lower or non-existing for either reason, it appears that the parts are extremely overvolted from the factory. The truth of course being that they are configured for perfectly right default voltage, which complies with the specifications (droop) and contains some standard safety margins.

On AM4 the situation is significantly better, since the load-line spec. is less than half of what it was on AM3+.
The Stilt said:
AM4 requires much beefier VRMs (all CPU / APU planes), higher quality PCB (due higher currents, faster signaling), etc. The design guidelines for all Zen based platforms are quite demanding, so you cannot get away with the same garbage quality as one could with "AM1" or FM2+. Unless you want to break the platform cross compatibility of course. All FM2+ boards < 60$ (CSP) are generally garbage and in most cases cannot operate properly with all the APUs available for the platform.
 

Lorne

Senior member
Feb 5, 2001
874
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HT or SMT will always be the better until they perfect programming and compiling.
Bios control on/off need or preferred, Software on the fly would be cool.
Actually bios or software variable input control dynamic HT would be great.
But for now HT would be best to have, Even the game benchmark above show that HT would help the FX a lot.
 

coercitiv

Diamond Member
Jan 24, 2014
4,166
5,069
136
Interesting poll results. 50/50 split (51.9% yes, 48.1% no)
Undecided voters are just that, undecided. Don't put them in another category they did not choose to begin with.

46.1% said Yes
28.9% said No
25% said they don't know
 

superstition

Platinum Member
Feb 2, 2008
2,219
216
101
Undecided voters are just that, undecided. Don't put them in another category they did not choose to begin with.

46.1% said Yes
28.9% said No
25% said they don't know
That's your opinion. Mine is that when people say yes, even if they're not completely sure, it goes into the yes category.

There is a special category for people who are completely undecided, making your objection a bit silly in my view.
 

coercitiv

Diamond Member
Jan 24, 2014
4,166
5,069
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That's your opinion.
It's not opinion, it's fact.

Opinion is when you take it upon yourself to place people who answered "Not sure" in the "Yes" category simply based on their nuanced answer. Opinion would also be if someone were to take this poll data, discard every answer starting with "Not sure", and claim more than 60% of people who were decided on the issue are in favor of the product.
 

superstition

Platinum Member
Feb 2, 2008
2,219
216
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Opinion is when you take it upon yourself to place people who answered "Not sure" in the "Yes" category simply based on their nuanced answer. Opinion would also be if someone were to take this poll data, discard every answer starting with "Not sure", and claim more than 60% of people who were decided on the issue are in favor of the product.
Thanks for your opinion once again.
 

KTE

Senior member
May 26, 2016
478
130
76
Personally speaking, I wish they would make these CPUs with mix and match of multiple uarchs.

2 highly clocked Cores, 2 somewhat lower and 8 normally clocked Cores.

Sent from HTC 10
(Opinions are own)
 

TheELF

Diamond Member
Dec 22, 2012
3,194
365
126
Personally speaking, I wish they would make these CPUs with mix and match of multiple uarchs.

2 highly clocked Cores, 2 somewhat lower and 8 normally clocked Cores.

Sent from HTC 10
(Opinions are own)
That's turbo,they downclock some cores to make the rest faster.
 

KTE

Senior member
May 26, 2016
478
130
76
That's turbo,they downclock some cores to make the rest faster.
Nah.

Different uarchs. SHP + SLPP uarchs mixed. Think big.LITTLE. More serial -> first 4 cores, 4.5/4.5/4.0/4.0. More parallel -> other 8/10 cores.

Sent from HTC 10
(Opinions are own)
 

TheELF

Diamond Member
Dec 22, 2012
3,194
365
126
Yeah task manager would love this,everything would run like crap for like 2-3 years until M$ fixes it.
 

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