[DigiTimes] TSMC 10 nm trial production in 2015, mass production in 2016

[witeken]

Don't take this the wrong way, but do you know any Intel process dev engineers? Meaning have you had a chance to talk with one recently?

[etc.]

IEMD isn't exactly meant for the big public. If you dig deep enough, I think you are able to get a picture that's not too bad. Bohr said they don't expect problems with 10nm, the node technology has been pinned down since 2012. You might call me naive that I take his word in this.

Your Intel timeline seems fantastically optimistic.

TSMC garners >21% of their revenue from 20nm. Do you think >21% of Intel's revenue is from 14nm? 20nm is here in big volumes, they just helped Apple bag $18B in quarterly profits.

Only because the world's richest company is their customer and doesn't give a damn about yields and wafer costs. But how many Qualcomm phones, how many GPUs and CPUs have you seen with 20nm? None.

What did 14nm do for Intel in Q4?

Personally I haven't laid my eyes on a single Intel 14nm processor. Have only seen a few integrated mobile devices containing them.

Newegg doesn't even list 14nm as an option when you use powersearch. Where are you getting the impression or data to support an argument that 14nm is here in big volumes? (serious question, did they discuss it in their recent earnings CC?)

14nm has been in HVM since mid-'14. Many laptops have been announced at CES and it will be their fastest node transition ever.

 

[III-V]

IEMD isn't exactly meant for the big public

Yes, however you have to keep in mind who's paying attention -- it's going to be the engineers from Intel's competition.

Only because the world's richest company is their customer and doesn't give a damn about yields and wafer costs. But how many Qualcomm phones, how many GPUs and CPUs have you seen with 20nm? None.

Apple absolutely cares about cost -- they're notoriously picky. TSMC's margins are super slim on the wafers they sell Apple.

 

[witeken]

Yes, however you have to keep in mind who's paying attention -- it's going to be the engineers from Intel's competition.

Apple absolutely cares about cost -- they're notoriously picky. TSMC's margins are super slim on the wafers they sell Apple.

Okay, I take all my statements back.

 

[Fjodor2001]

Claim: "Intel's 10nm will go into production in Q4".
Claimed source: "10nm production: IM'13"

Obsolete info replaced by Early 2017 release estimate for 10 nm by Intel here.

Claim: "Early work on TSMC's 10nm will be started at the end of the year [2016]. Volume production 2017"
Claimed source: "TSMC earnings call of some days ago."

Link to that? The article in the OP says TSMC trial production in 2015, mass production in 2016. How does that match with your info?

Claim: "Volume production 2017, which is the same year 7nm is planned to go into production (usual disclaimer)"
Claimed source: "7nm: extrapolation from 2 year Tick-Tock cadence and slides from Intel (but usual disclaimer that actual dates may vary materially since these are forward looking statements...)"

So you're just guessing then.

 

[NTMBK]

14nm has been in HVM since mid-'14. Many laptops have been announced at CES and it will be their fastest node transition ever.

It's only going to be such a fast transition because it was delayed for so long in the first palce How many laptop designs do you think OEMs have had ready for months, waiting for Intel to get Broadwell yields high enough to ship?

 

[witeken]

Link to that? The article in the OP says TSMC trial production in 2015, mass production in 2016. How does that match with your info?

The OP is obsolete.

So you're just guessing then.

Just for fun: CTRL+F "year" in

http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_presentation.pdf

Ignoring 14nm for a second, which really is an exception to the rule, Intel has an unprecedented, in fact the best, track record of the whole industry. Intel will not slow down, so my expectations are set accordingly, since Intel set the bar that high themselves. We'll see how they execute at this nanoscale in the coming years, but let me remind you of:

TSMC looks tiny in comparison!

 

[Arachnotronic]

Yes, however you have to keep in mind who's paying attention -- it's going to be the engineers from Intel's competition.

Apple absolutely cares about cost -- they're notoriously picky. TSMC's margins are super slim on the wafers they sell Apple.

Not that slim...TSMC's corporate margin was like 50% in the last quarter, and 20% of that was 20nm wafers probably mostly going to Apple!

 

[witeken]

Another company "catching up" with Intel on 14nm: UMC

http://www.eetimes.com/document.asp?doc_id=1325455&

UMC is intensifying efforts to catch up with the world’s leading foundry, Taiwan Semiconductor Manufacturing Co. (TSMC), which raised its capital expenditure budget for 2015 to US$11.5-12.0 billion, up 11.5-20.0 percent from 2014, mainly due to the company’s expectation of stronger demand for advanced geometries. UMC is nibbling away at the 28nm segment, while TSMC is on schedule to start volume production of 16nm FinFET products by the second quarter of this year.

UMC said it expects its first tapeouts of 14nm products by the second quarter of this year.

Edit: An article on 10nm:

http://semiengineering.com/first-look-10nm/

 

[III-V]

Not that slim...TSMC's corporate margin was like 50% in the last quarter, and 20% of that was 20nm wafers probably mostly going to Apple!

Well, perhaps not "super" slim, but I can't imagine they'd be very large.

 

[imported_ats]

Well, perhaps not "super" slim, but I can't imagine they'd be very large.

Yeah its probably a bit of a double edged sword. Apple was willing to guarantee a large early order (probably one of the largest ever single orders for a leading edge process at TSMC) and probably with money up front. But I wouldn't be surprised that if as part of that order a large portion of the yield variance liability is on the TSMC side. After all, Apple's order appears to be the largest first quarter production volume order TSMC has ever gotten at least from looking at their historical process mix charts.

 

[Exophase]

TSMC looks tiny in comparison!

That's not a fair comparison and you know it. TSMC isn't in most of the markets Intel is in. I'm sure if I put Samsung on that graph (which would eclipse even Intel) you'd call foul.

 

[Arachnotronic]

That's not a fair comparison and you know it. TSMC isn't in most of the markets Intel is in. I'm sure if I put Samsung on that graph (which would eclipse even Intel) you'd call foul.

I wouldn't say eclipse but yes, Samsung's R&D came in at about $13 billion last year against Intel's $11 billion.

But yeah, comparing a pure play foundry to an IDM is as apples to oranges as it gets...

 

[Fjodor2001]

http://www.eetimes.com/document.asp?doc_id=1325787

TSMC to Start 10nm in 2017, Closing Gap with Intel

TAIPEI — Taiwan Semiconductor Manufacturing Co. (TSMC), the world’s largest chip foundry, said that it expects to start 10 nanometer production in 2017, when it will have process technology matching that of industry leader Intel Corp.

“The performance of our 10nm, in terms of speed, power and density will be equal to what we believe Intel will define as its 10nm technology,” TSMC Director of Corporate Communications Elizabeth Sun told EE Times. “Technology-wise, we think we can close the gap at 10nm.”

For the first time this year, TSMC is expected to have the largest capex in the semiconductor industry as it aims to maintain its lead in the foundry business against rivals such as Samsung, Intel and Global Foundries.

TSMC has raised its capital expenditure budget for 2015 to US$11.5-12.0 billion, an increase of 11.5-20.0 percent compared with 2014, mainly due to its confidence in demand for advanced geometries. Intel spent $10.1 billion on capex during 2014. For the current year, Intel expects that figure to hold steady, at $10 billion, plus or minus $500 million.
[...]
By the end of 2018, the company’s Taichung site will reach a monthly output capacity of 90,000 wafers at the 10nm and more advanced technology nodes, according to a report on the Chinatimes.com website.

 

[ShintaiDK]

To make an example of TSMCs PR spins. 90000 wafers a month is around what the development fab in Oregon makes. And thats what TSMC expects to reach in the end of 2018. The D1X(Module 1) in Oregon is around 150000 wafers per month.

 

[witeken]

To make an example of TSMCs PR spins. 90000 wafers a month is around what the development fab in Oregon makes. And thats what TSMC expects to reach in the end of 2018. The D1X(Module 1) in Oregon is around 150000 wafers per month.

90.000 is quite a nice number, quite a bit of SoCs. But I would be skeptical about such forward looking statements many years in the future.

 

[mavere]

TSMC's 20nm output by the end of 2014 was presumed to be ~70k wpm.

I don't want to read too much into a PR, but at face value, 90k on a leading node with the expected $/mm2 scaling is lots and lots of revenue.

 

[zebrax2]

To make an example of TSMCs PR spins. 90000 wafers a month is around what the development fab in Oregon makes. And thats what TSMC expects to reach in the end of 2018. The D1X(Module 1) in Oregon is around 150000 wafers per month.

I don't know TSMCs ramp up for 20nm seems to be doing phenomenal judging by this post of IDC.
http://forums.anandtech.com/showpost.php?p=37195818&postcount=174

 

[Idontcare]

To make an example of TSMCs PR spins. 90000 wafers a month is around what the development fab in Oregon makes. And thats what TSMC expects to reach in the end of 2018. The D1X(Module 1) in Oregon is around 150000 wafers per month.

Are they 90kwpm of development wafers (10nm and 7nm) or are they 90kwpm of 14nm production being handled in what Intel otherwise labels as a development fab?

If they are all development wafers then they can't be full-flow wafers, they must be counting short-flow test wafers in that tally as well.

I'd be very impressed if Intel's R&D team is running even 1/10 that amount of full-flow development WIP for 10nm at this time. 300 wafers per day is a LOT of development material, let alone 3000 wafers per day which you are suggesting they are running in D1D.

 

[Idontcare]

http://www.eetimes.com/document.asp?doc_id=1325787

I was impressed to see TSMC will eclipse Intel in terms of capex. Business is booming for them and they continue to see the need to establish a huge amount of capacity for 16FF+, let alone 10nm.

I can accept their 10nm timeline, it is reasonable. But I find it difficult to accept their claims of matching or near-matching Intel's parametric FOM and design rules.

You don't just get there by making it a milestone on a presentation and giving your engineers 3-4 years to deliver on something your competitor has spent a decade or so investing to enable their employees to achieve. Not on TSMC's R&D budget anyways, project management triangle conundrum that one.

 

[ShintaiDK]

Are they 90kwpm of development wafers (10nm and 7nm) or are they 90kwpm of 14nm production being handled in what Intel otherwise labels as a development fab?

If they are all development wafers then they can't be full-flow wafers, they must be counting short-flow test wafers in that tally as well.

I'd be very impressed if Intel's R&D team is running even 1/10 that amount of full-flow development WIP for 10nm at this time. 300 wafers per day is a LOT of development material, let alone 3000 wafers per day which you are suggesting they are running in D1D.

I assume the wast majority is 14nm. But its more a size example if TSMC expets 80000 in the end of 2018 on 10nm. Then its really not much. And more PR than its actual production. Specially to claim parity in 2017 where the volume must be much lower for them.

 

[teejee]

I assume the wast majority is 14nm. But its more a size example if TSMC expets 80000 in the end of 2018 on 10nm. Then its really not much. And more PR than its actual production. Specially to claim parity in 2017 where the volume must be much lower for them.

You're making a mistake here, one 300mm wafer is at least 500 100mm2 SOC's (I e high end SOC's). So 90000 wafer a month is more than 500 million high end SOC's a year, that is a huge amount regardless what you compare with.

 

[witeken]

You're making a mistake here, one 300mm wafer is at least 500 100mm2 SOC's (I e high end SOC's). So 90000 wafer a month is more than 500 million high end SOC's a year, that is a huge amount regardless what you compare with.

You're off by 1 order of magnitude, and whether you have 400 or 500 SoCs per wafer depends on the yields.

 

[ShintaiDK]

You're making a mistake here, one 300mm wafer is at least 500 100mm2 SOC's (I e high end SOC's). So 90000 wafer a month is more than 500 million high end SOC's a year, that is a huge amount regardless what you compare with.

Not really. And you only have to look at 20nm to see how wrong your assumption is due to yield.

Lets look at the bigger picture. First of all the 80000 wafers per month is only in the end of 2018. Thats already way behind. Who knows what they will make in 2017 and at what yields. But its certainly a lot less than 80000.

For Intel, mass production on a leading edge node starts with around 100000 wafers a month with reasonable high yields. 14nm for Intel is most likely already in the 250000-300000 wafers a month range and still ramping with 5 fabs making 14nm wafers in x volumes, 3 of them more or less dedicated to 14nm including the D1X Module 1 with a capacity of 150000 wafers a month.

For 10nm, I am sure Intel will already be making more 10nm wafers per month in the end of 2016 than TSMC will in the end of 2018.

This also shows one of the issues TSMC, Glofo and Samsung have to deal with and pass on to their customers with higher transistor cost below 28nm.

Those 10nm chips will cost a truckload more than 10nm chips at Intel.

 

[Nothingness]

You're off by 1 order of magnitude,

No he isn't: 90k*500*12=540M.

and whether you have 400 or 500 SoCs per wafer depends on the yields.

100mm2 means 600 chips per wafer and Intel yield are supposedly excellent.

 

[ShintaiDK]

No he isn't: 90k*500*12=540M.


100mm2 means 600 chips per wafer and Intel yield are supposedly excellent.

But thats before yield. Not to mention if the chips can actually perform as required or not. Its quite obvious from 20nm that the amount of theoretical chips and actually useable chips is a completely different world.