Not completely sure what you mean with that.
Heaviside step function
What most people invoke as a "quantum leap" is really more appropriately described as a Heaviside step function whenever the individual invoking the phrase "quantum leap" is doing so to imply a gap or step-up in whatever is being discussed versus the less relevant equivocation of the physics entailed in a quantum transition.
If you are looking for a specific example, TSMC doubled their entire R&D team (headcount and resources) for 10nm development.
I suspect TSMC and Samsung's 10nm will compete against Intel's 7nano-units for most of their bleeding edge lifetime. I also suspect many people will uncritically think Intel's technology lead has been eroded away.
2 years ago I would have taken that bet. But I'm not seeing Intel running the same way under BK that it did under Otellini. I think we are going to see 10nm run head-to-head, and then 7nm, etc., even if by virtue of marketing manipulation of the node label. If Intel gets too far ahead, again, then the foundries will just pull another 16/14nm out (claim a new node exists where none was before) and they'll be back to "node parity".
As for those who will rush to internalizing that as an erosion in Intel's lead...true but that is Intel's problem. Intel has no issue
hyping their technology prowess for the benefit of analyst and shareholder alike. I'm confident they won't sit idly by and let their shareholders and analysts down. They'll find a marketing way to ensure the market is fully and properly educated on why their 10nm (or 7, or 5) is superior to the competition's.
I wonder if EUV will be first deployed at 10,000pm and by which company first.
Ha ha, 10,000pm

We stuck fast to the micron node label well near the 0.1um node before finally switching vernacular and referring to them in nanometer units. Even the early days of 90nm development it was still referred to as 0.09um. I doubt we'll ever see nm node labeling give way to pm node labels, the numbers are just to big to make for good marketing.
It will be nm all the way down to 0.1nm (equivalence, of course, the same as we use for gate oxide scaling which is given an EOT rating in Angtroms).
EUV, if it happens in production at 10nm, will likely be limited to just a single litho step at the very most critical mask in the entire flow, with all the remaining less-critical (but still paramount) masks being done in 2, 3 or 4 multi-patterning. But it is a necessary "first" for EUV to gain the production environment time it needs to work out all the gatekeeping issues before full production rollout at 7nm can happen.
Hmm... how come? Latest info is that both Intel and TSMC will release 10 nm to the public in 2017 (although those 10 nm process techs will have different characteristics). Can Intel really release 7 nm almost at the same time as 10 nm?
Intel could, but nothing is keeping TSMC and Samsung from deciding they are skipping 10nm and are going to go straight to 7nm...the key being their 7nm would look surprising similar to what they were previously calling their 10nm node :hmm: :sneaky: (kinda like how 16FF/14nm look an awful lot like what they should have delivered with their 20nm nodes in the first place...)