Delidded my i7-3770K, loaded temperatures drop by 20°C at 4.7GHz

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Dufus

Senior member
Sep 20, 2010
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Two things can be happening, and possibly in combination.

One is the push-pull pumping effect that comes with the mechanical expansion and contraction of the silicon, the TIM, and the overhead IHS. Eventually, given time, the TIM itself will be squeezed out of the gap that it occupies between the die and the IHS and an air gap will be left in its place. The air gap most likely forms when the CPU cools down.

Push-pumpTIMgap.png


Then when the CPU heats back up, the air gap prevents the IHS from heating up in concert with the die and the TIM, resulting in an IHS that is not expanding to fill in the air gap, leaving the CPU much hotter than before.

The second point of concern is that of emulsion separation - the molecular components that comprise NT-H1 may experience separation at the behest of the silicon die interaction (it will actually be a silicon nitride at the surface). NT-H1 was probably not designed to remain an emulsion when in contact with silicon as it was designed to remain an emulsion when in contact with copper, aluminum, or nickle (more specifically, the metal oxides of those elements).

So a chemical separation may be the culprit as well, and likely it is a combination of both.
Idc just a thought, I remember some of the older IHS's had a small hole maybe to allow for air expansion, pressure build up. Idk if the IVB IHS is purged when assembled. Do you think this could be an effect when reassembling the IHS?
 

ShadowVVL

Senior member
May 1, 2010
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I don't know if this has been asked yet but have you tried a custom loop with swiftech water block and 4x120mm rad?
 
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Yuriman

Diamond Member
Jun 25, 2004
5,530
141
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That's basically what I have. These chips really don't put out much heat though, the rad doesn't need to be very big. I'm waiting for some kind of verdict on TIM before I pop my lid.
 

chuck1723

Junior Member
Aug 25, 2009
10
0
66
I would like to see results from direct contact from hsf and the processor die. I would think that would give the best results.
 

BonzaiDuck

Lifer
Jun 30, 2004
15,699
1,448
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I would like to see results from direct contact from hsf and the processor die. I would think that would give the best results.

Perhaps we'd all like to see that, but it wouldn't be my top priority. It's bad enough that a modder-enthusiast has to remove the IHS; worse that we're not yet sure that some choice of TIM replacement won't have a degraded effect over time; and worse than that if we have to mod the motherboard clip irreversibly to accommodate a direct contact between HSF base and CPU-die.

Then there's the horror beyond worse, if the odds of damage to the die rise to a point that seriously lowers the expected value of the processor you bought in the first place. In other words, so risky as to deter doing it at all.
 
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rge2

Member
Apr 3, 2009
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Guys at Puget Systems gave it a shot. Seems that temperature drop from changing the TIM might not be as drastic as reported on forums. Culprit could be a bad application the stock TIM during manufacturing. And somehow they managed to damage a cpu (even with care). . So in their opinion it might be not worth the risk.

pic_disp.php


http://www.pugetsystems.com/labs/articles/Ivy-Bridge-CPU-TIM-Paste-Replacement-160

What a waste of 3 cpus on a sloppy experiment.

They only tested at stock v core and near stock vcore. They did stock and then added only 0.045 vcore. So stock is ~1.1v at max and their overclock was 1.15 vcore at max (probably lower). The fact they got the same ~2C difference should have clued them in they needed to actually overclock with higher vcore first, because IVY doenst have a temp problem at/near stock. Then they realized they could overclock further to 4.7 with changed tim....but did not check temps prior with that 4.7, and even then they added less than 0.1vcore, so still at near stock volts, maybe 1.2v?

But given they allowed mobo to control fan speed and they ran furmark along with prime????, so they had no clue of an accurate temp change, perhaps it is best they didnt do an appropriate experiment. Then even after they realized the varying fan speed might be an issue, instead of connecting the fans to a steady 12v supply, they tried to average fan speeds as a control after the fact, and found the changed tim had lower fan speeds by 80rpms, but concluded it wasnt probably significant.

Then the realized the could overlclock 200mhz higher, but didnt check before temps.

What a waste of 3 cpus. And I dont see they found much different than anyone else if they had measured difference at stock volts if given the several C error added in. And my guess they were not actually stable at those volts. I can run all day and 2 hrs prime at 0.1 vcore less than what I need for prime 12hrs stable.
 

mrob27

Member
Aug 14, 2012
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Yeah I've still got a number of tests planned.

I'm currently hung-up on attempting to get the gap between the CPU and the IHS to be the same as it was before I delidded the CPU.

That way I can generate some apples-to-apples data for comparing the thermal properties of Intel's stock CPU TIM versus that of the other 3rd party TIM's we have at our disposal.
[...]

If I had the equipment and money to be doing these sort of tests I'd be shimming with the "plastic" from plastic shopping bags, because it's thin, slides easily, and doesn't conduct electricity.

I want to remind you that it's easy to measure the thickness of many materials by folding it over and over again and dividing the measurement by the appropriate number.

If your time is limited, I think I'd rather know what we get from using a shim that's as close as possible to the smaller value (0.14mm) rather than the original 0.20mm (both figures based on your "mind the gap" work).
 

BonzaiDuck

Lifer
Jun 30, 2004
15,699
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What a waste of 3 cpus on a sloppy experiment.

They only tested at stock v core and near stock vcore. They did stock and then added only 0.045 vcore. So stock is ~1.1v at max and their overclock was 1.15 vcore at max (probably lower). The fact they got the same ~2C difference should have clued them in they needed to actually overclock with higher vcore first, because IVY doenst have a temp problem at/near stock. Then they realized they could overclock further to 4.7 with changed tim....but did not check temps prior with that 4.7, and even then they added less than 0.1vcore, so still at near stock volts, maybe 1.2v?

But given they allowed mobo to control fan speed and they ran furmark along with prime????, so they had no clue of an accurate temp change, perhaps it is best they didnt do an appropriate experiment. Then even after they realized the varying fan speed might be an issue, instead of connecting the fans to a steady 12v supply, they tried to average fan speeds as a control after the fact, and found the changed tim had lower fan speeds by 80rpms, but concluded it wasnt probably significant.

Then the realized the could overlclock 200mhz higher, but didnt check before temps.

What a waste of 3 cpus. And I dont see they found much different than anyone else if they had measured difference at stock volts if given the several C error added in. And my guess they were not actually stable at those volts. I can run all day and 2 hrs prime at 0.1 vcore less than what I need for prime 12hrs stable.

To reach that level of a control on the observations, you'd want to look either at a set of speeds and vcores that had been vetted for 24/7 operation, or you might try to find the point where each of those speed/vcore pairs would all fail after some amount of time -- say -- an hour. The more "misses" it takes to find a "hit" for each speed, the more time you will consume. And obviously, stressing for 24/7 reliability also takes time.

And I'm trying to remind myself that we're talking about measuring temperatures for TIM comparisons for the de-lidding project. Yeah -- that sounds right . . .
 

rge2

Member
Apr 3, 2009
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0
0
I would have been happy had they just tested at stock settings, and then 1 legitimate overclocked speed of 4.7 or 4.8 with vcore necessary for prime stable...not artificially low vcore for given mhz that they would never actually use for stable, that would only serve to show same few C gain as stock settings. They used 4.5ghz with 1.1ish vcore.

For example, just making up numbers for illustration sake, but changing better tim then testing at/near stock vcore only expect few C improvement in temps, then at 4.5ghz with actual vcore for stable of 1.25ish maybe ~7C decrease in temps, 4.7ghz 1.35v over 12C improvement etc.

But they tested stock vcore, twice, and nothing else, then suggested that temps dont improve as much on legitimate overclocks as others claim...without ever testing in same range where physics would allow, and others saw the larger decrease in temps.
 
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Idontcare

Elite Member
Oct 10, 1999
21,118
58
91
For example, just making up numbers for illustration sake, but changing better tim then testing at/near stock vcore only expect few C improvement in temps, then at 4.5ghz with actual vcore for stable of 1.25ish maybe ~7C decrease in temps, 4.7ghz 1.35v over 12C improvement etc.

But they tested stock vcore, twice, and nothing else, then suggested that temps dont improve as much on legitimate overclocks as others claim...without ever testing in same range where physics would allow, and others saw the larger decrease in temps.
Just going to point out the obvious here - these guys have a HUGE conflict of interest when it comes to these tests.

They sell pre-overclocked systems, and they compete against a world full of DIY'er OC'ers who aren't interested in paying a premium to buy someone else's pre-overclock build.

And that works when they can buy a $25 performance tuning warranty so they don't have to eat the cost of one of their customers killing their overclocked processor.

But if they have to start competing with delidded processors that reach OC's and temperatures unobtainable by conventional OC'ing then that is a business vector they can't pursue. They can't start shipping delidded processors without taking on HUGE economic liability of those CPU's dying in the field without warranties (the intel plan doesn't cover CPU's that have been physically tampered with).

So they really need this whole delidding fad to be just that, something that can be safely ignored while they continue convincing their customers that they don't need a delidded IB for hitting higher OC's or having better temperatures.

I'm not financially benefiting from these results, nor do I stand to have my financial livelihood put into jeopardy if delidding really does deliver a new tier in performance for the enthusiast. The same cannot be said of the folks who underwrote that quality piece of work that purports to debunk the benefits of delidding.

In many ways this is a reminder of why review sites like AnandTech got started in the first place. There was huge conflict of interest between hardware providers and ad agencies in the traditional print circles, but the web enable a whole generation of independent reviewers to approach hardware reviews without the need to grease a bunch of palms and scratch everyone's backs.
 
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BonzaiDuck

Lifer
Jun 30, 2004
15,699
1,448
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Just going to point out the obvious here - these guys have a HUGE conflict of interest when it comes to these tests.

They sell pre-overclocked systems, and they compete against a world full of DIY'er OC'ers who aren't interested in paying a premium to buy someone else's pre-overclock build.
. . . .
In many ways this is a reminder of why review sites like AnandTech got started in the first place. There was huge conflict of interest between hardware providers and ad agencies in the traditional print circles, but the web enable a whole generation of independent reviewers to approach hardware reviews without the need to grease a bunch of palms and scratch everyone's backs.

:thumbsup::thumbsup:

Posi-lutely, Abso-tively. People need to understand these things. I've seen it in magazine comparison reviews, in which the competing products are handpicked to avoid mention of products that would have otherwise won in the comparison. Often the review article is followed by an advertisement page plugging the "winning" product.

There are all sorts of situations where these conflicts of interest occur, and all or most can be boiled down to the factors you cite in your response to the example.
 

rge2

Member
Apr 3, 2009
63
0
0
Just going to point out the obvious here - these guys have a HUGE conflict of interest when it comes to these tests.

They sell pre-overclocked systems, and they compete against a world full of DIY'er OC'ers who aren't interested in paying a premium to buy someone else's pre-overclock build.

And that works when they can buy a $25 performance tuning warranty so they don't have to eat the cost of one of their customers killing their overclocked processor.

But if they have to start competing with delidded processors that reach OC's and temperatures unobtainable by conventional OC'ing then that is a business vector they can't pursue. They can't start shipping delidded processors without taking on HUGE economic liability of those CPU's dying in the field without warranties (the intel plan doesn't cover CPU's that have been physically tampered with).

So they really need this whole delidding fad to be just that, something that can be safely ignored while they continue convincing their customers that they don't need a delidded IB for hitting higher OC's or having better temperatures.

I'm not financially benefiting from these results, nor do I stand to have my financial livelihood put into jeopardy if delidding really does deliver a new tier in performance for the enthusiast. The same cannot be said of the folks who underwrote that quality piece of work that purports to debunk the benefits of delidding.

In many ways this is a reminder of why review sites like AnandTech got started in the first place. There was huge conflict of interest between hardware providers and ad agencies in the traditional print circles, but the web enable a whole generation of independent reviewers to approach hardware reviews without the need to grease a bunch of palms and scratch everyone's backs.

yep, my thoughts exactly. And I am just making sure everyone else that sees the headlines of their article but doesnt read it, knows they set up the test to get the result they wanted, and not to test for knowledge as your are doing.
 

C.C.

Member
Aug 21, 2012
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0
I would like to see results from direct contact from hsf and the processor die. I would think that would give the best results.

Never fear, CC is here!..After dealing with some real life health issues that love to get in the way every time I attempt something, I have finally got in the much anticipated IC Diamond, along with a Kill Coil for my loop! I hope to have everything together tonight to get it leak tested/bled, and then we will be off to the races for some direct die cooling!

My plan is to run the IC diamond @ my max possible OC for a period of at least 2 weeks, checking for temperature spikes once I find my max IBT 24/7 stable OC..after I have determined if the IC Diamond stays the same, or suffers from the reversion that some other pastes have (see Ferp's testing), then I will go from there...

I still plan on testing the Arctic Cooling MX-2 since I have it, and AC claims it has a high carbon base...I will test the two @ various speeds and voltages to try to get an Apples to Apples comparison..

The only thing that I am worried you guys might not like is the fact that my GTX 480 has to be in the same loop as my cpu...I only have a single Swiftech MCP 655B pump, but I do have both a 360mm and a 120mm rad with excellent Airflow to offset the heat the gpu dumps into the loop (Gentle Typhoon AP-15s in my HAF 932)..

Pictures will be up tomorrow or Tuesday @ the latest, including detailed shots of the removal of the stock retention bracket and my DIY mounting.
 

mrob27

Member
Aug 14, 2012
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www.mrob.com
I'll refer to my previous posts in this thread, which you can find here:

Update:

Since my speculation about tweaks to the 22nm process we've gotten a leaked Ivy Bridge Xeon roadmap. Here is an article at WCCF Tech: Intel’s Leaked Roadmap Shows Ivy Bridge-EP/EN...

Of greatest interest to me is this image, which clearly shows a representative Xeon in each market segment (vertical axis) and microarchitecture (horizontal axis) going from the original Nehalem to Ivy Bridge. (At the bottom, the existing Xeon E3 is not included). The clocks speeds are all really low because for some reason they're showing the slowest Xeon in each category. See Wikipedia's http://en.wikipedia.org/wiki/List_of_Intel_Xeon_microprocessors for more.

With Ivy Bridge-EP, it appears that they're expanding the socket 1356/2011 platform to extend from single-socket workstations up to 4-socket servers (other leaks at about the same time indicated that the high-end E7-2800/4800/8800 family is expanding upwards too, offering more than 8 sockets without glue logic).

That roadmap really doesn't tell us much, because it only shows the number of cores and TDP for each market segment, which is not enough to figure out if they're targeting higher clock speeds. But it's worth noting that they're going to to 12 cores in some cases, and that most, but not all, of the segments will have more cores. I have no idea what impact if any this will have on the successor to the Core i7-3960X.

More important by far was Mark Bohr's session at IDF, session SPCS008. Go to the session catalog, find SPCS008 and click on the tiny PDF icon to get the slides.

The missing drive current chart that we noticed before is here, sort of, in slide 34:

bohr-20120912-sl34.png


If you compare to the charts in my earlier post you'll see that these drive currents are much lower. But it's also a lower voltage (0.75V) than the earlier charts, which are all for 1.0V. So I don't think it compares. Also, it's for the upcoming 22nm SoC process, which includes a wider range of transistors than the first 22nm process, but that's okay as long as we're looking at the "HP" (high performance) part of the curve.

There's also this slide:

bohr-20120912-sl20.png


I've seen charts like this before but I don't know what to make of them. Perhaps IDC or others in this thread can tell whether it is useful. DIBL is drain induced barrier lowering and appears as the spacing between the 0.05V and 0.8V curves where they are parallel and straight. It's one of those scary short-channel effects I mentioned before.

There was also a session on overclocking, PCES003 (use the catalog link above), which looked pretty good. It was encouraging, particularly the statements at the end (see slide 67) committing to continue supporting overclocking and bring new features (like the 3960X's BCLK ratios) to more products.
 
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BonzaiDuck

Lifer
Jun 30, 2004
15,699
1,448
126
Never fear, CC is here!..After dealing with some real life health issues that love to get in the way every time I attempt something, I have finally got in the much anticipated IC Diamond, along with a Kill Coil for my loop! I hope to have everything together tonight to get it leak tested/bled, and then we will be off to the races for some direct die cooling!

My plan is to run the IC diamond @ my max possible OC for a period of at least 2 weeks, checking for temperature spikes once I find my max IBT 24/7 stable OC..after I have determined if the IC Diamond stays the same, or suffers from the reversion that some other pastes have (see Ferp's testing), then I will go from there...

I still plan on testing the Arctic Cooling MX-2 since I have it, and AC claims it has a high carbon base...I will test the two @ various speeds and voltages to try to get an Apples to Apples comparison..

The only thing that I am worried you guys might not like is the fact that my GTX 480 has to be in the same loop as my cpu...I only have a single Swiftech MCP 655B pump, but I do have both a 360mm and a 120mm rad with excellent Airflow to offset the heat the gpu dumps into the loop (Gentle Typhoon AP-15s in my HAF 932)..

Pictures will be up tomorrow or Tuesday @ the latest, including detailed shots of the removal of the stock retention bracket and my DIY mounting.

I don't think the complications of your water-cooling rig have much bearing on the value of what you might show us later. We know that diamond paste will perform better than Arctic Silver, and not that much worse than a "liquid metal" or metal-pad solution. What we want to see are your load temperatures after initial installation (assuming you "get it right" and they show serious improvement over the stock Intel TIM), and load temperature readings under the same conditions after several shutdowns and re-boots with the same CPU loading after various periods of time -- over a month or so. I would guess that we would know for sure that the diamond paste is a stable solution after such a workout and time-lapse.

The key thing we're looking for is any sign of a significant degradation from point of initial diamond-TIM application due to "pumping out" or "voids" and so forth. You might be able to accomplish the same thing in a couple weeks, but you'd have to keep your attention on it, going through the paces of cooling and heating several times and loading up the processor at least as many times.
 

Nemesis 1

Lifer
Dec 30, 2006
11,366
2
0
It costed me a bit moreto do mine than what you did , I had mine lid off and had it machined down so that the processor was a half a thousand taller than the lid. I mounted my waterblock directly on the die used the lid as a lock down and to stop rocking on the die only . I setting at 5.1 ghz very pleased with my temps . I can talk about it now since haswell is on the horizon . Clearly I don't tell people what I do for sometime after the fact . Why should I ?
 

C.C.

Member
Aug 21, 2012
28
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0
*Snip*
The key thing we're looking for is any sign of a significant degradation from point of initial diamond-TIM application due to "pumping out" or "voids" and so forth. You might be able to accomplish the same thing in a couple weeks, but you'd have to keep your attention on it, going through the paces of cooling and heating several times and loading up the processor at least as many times.*SNIP*

I got everything together, but had to remove part of the loop due to a leak in my cpu block..This is the second time this has happened, and it is actually a problem with the way Enzotech designed the block..

If you use their included barbs, everything is fine, since they are the standard G 1/4 thread, but they are threaded nearly 60-70% longer then my BitsPower Compression fittings..This means that you don't get a good seal if using aftermarket barbs..It really is a shame since this is still one of the top 3 blocks on the market in relation to flow rate and cooling potential, and number one in terms of cost vs. performance!

I was able to get the leak fixed up, re-assembled the loop, and leak tested/bled it for 24hrs without an issue..I am reinstalling Windows 7 now, and will get some pictures uploaded once that is complete!..

Testing wise, I am an avid Folder B.D., so my plan was to Fold some test Work Units using a F@H stability program a friend @ [H] developed for us..F@H stresses the cpu way more then any other stability program, and generates the highest CPU temps I have ever seen vs. Prime95/IBT..

I plan on running the cpu @ 100% load for 24 hrs after I find my max stable OC. then will shut it down overnight and will resume 100% the next day..I can do this for as long as you guys wish, and since I am at home all week (I have a 100% disability so I don't "work" outside the house), I think I can generate the data you are looking for rather quickly..

Of course, if there is anything special you want me to do, feel free to chime in and I'll gladly do it..Keep in mind that I do not have any "stock" data, other then the temps I observed while using the stock Intel HSF for a short period of time to make sure I did not have any DOA parts before switching to water..

It costed me a bit moreto do mine than what you did , I had mine lid off and had it machined down so that the processor was a half a thousand taller than the lid. I mounted my waterblock directly on the die used the lid as a lock down and to stop rocking on the die only . I setting at 5.1 ghz very pleased with my temps . I can talk about it now since haswell is on the horizon . Clearly I don't tell people what I do for sometime after the fact . Why should I ?
I have read, and re-read your post, and either I am stupid or cannot seem to grasp seveal things...

1. You said you had the lid off and had it "machined" down..I assume you mean that you removed the IHS, and that is what you had "machined" down to just a hair taller then the stock retention bracket's "lid"??

2. Your second statement makes it seem like you removed the IHS, and then you state that you mounted the cpu block directly to the die WITH the stock retention bracket STILL in place?

I took this statement to be a contradiction of the way I interpreted your first, in that the "LID" you had "machined" was NOT the IHS, but the "LID" of the stock retention bracket..Would you mind clearing up which of these statements is the way you did in fact proceed..Also, do you have any pictures?

3."Clearly I don't tell people what I do for sometime after the fact . Why should I ?"...

I'm a bit confused as to what this statement is referring to? The reason you "should" share things is to help benefit the other members here who do not have the ability (or Guts maybe :biggrin:) to do the things we do in search of the highest overclocks/best cooling methods..
 

dqniel

Senior member
Mar 13, 2004
650
0
76
It's been about three weeks since I put IC Diamond between the core and the IHS, and load temperatures are still vastly improved over the stock solution. I will update my old post in a moment to show details-

Thermal Cycling/TIM Failure Test

System Info:

3570K Delidded with IC Diamond between the die and IHS
ZT-10D HSF with Arctic Silver Ceramique between the IHS and the HSF
4.5Ghz @ 1.232v (after vdroop)

Delidded and IC Diamond applied 8/29/2012

After one week:
(9/4/2012)

Ambient temp - 25C
3570K max temps after Prime "blend" for 30 minutes - 67C, 76C, 74C, 73C

After three and a half weeks:
(9/22/2012)

Ambient temp - 22C
3570K max temps after Prime "blend" for 30 minutes - 62C, 72C, 71C, 69C

More results to come...

Also, my Coollaboratory's Liquid Ultra came in the mail today. I'm tempted to try it out, but my IC Diamond hasn't shown any drop in performance yet so I'm going to hold off I think. I'll either wait until it degrades or until I get bored/curious and try out the liquid metal approach.
 
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BonzaiDuck

Lifer
Jun 30, 2004
15,699
1,448
126
It's been about three weeks since I put IC Diamond between the core and the IHS, and load temperatures are still vastly improved over the stock solution. I will update my old post in a moment to show details-

Thermal Cycling/TIM Failure Test

System Info:

3570K Delidded with IC Diamond between the die and IHS
ZT-10D HSF with Arctic Silver Ceramique between the IHS and the HSF
4.5Ghz @ 1.232v (after vdroop)

Delidded and IC Diamond applied 8/29/2012

After one week:
(9/4/2012)

Ambient temp - 25C
3570K max temps after Prime "blend" for 30 minutes - 67C, 76C, 74C, 73C

After three and a half weeks:
(9/22/2012)

Ambient temp - 22C
3570K max temps after Prime "blend" for 30 minutes - 62C, 72C, 71C, 69C

More results to come...

Also, my Coollaboratory's Liquid Ultra came in the mail today. I'm tempted to try it out, but my IC Diamond hasn't shown any drop in performance yet so I'm going to hold off I think. I'll either wait until it degrades or until I get bored/curious and try out the liquid metal approach.

Two sets of numbers is hardly even a "Student's T" small-sample, but given the ambients, you can hardly say things have gotten worse after 3 and a half weeks.

Thanks for posting this.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
58
91
It costed me a bit moreto do mine than what you did , I had mine lid off and had it machined down so that the processor was a half a thousand taller than the lid. I mounted my waterblock directly on the die used the lid as a lock down and to stop rocking on the die only . I setting at 5.1 ghz very pleased with my temps . I can talk about it now since haswell is on the horizon . Clearly I don't tell people what I do for sometime after the fact . Why should I ?

The question isn't "why should I?"; rather, the question is "why are you now?"

I can understand not taking the time to document/upload the efforts it took to do what you did, not everyone has the energy or desire for such laborious endeavors.

But coming in after the fact just to make sure you set the record straight and get your name out there as being "top dog" is, well, is a bit braggadocious and unflattering of yourself.

If you solve world hunger but tell no one the solution then that doesn't make you any better than the people who don't even bother attempting to solve world hunger ;) And it certainly isn't anything you should bragging about after the fact either.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
58
91
Cool, thanks for the update :) I wouldn't mind seeing some fail pictures, I'm curious about what happened ;) Unless it takes too much of your time of course :)

Update on this: the reason I failed to upload the results as promised weeks ago is that I can't find my camera which has all the photos on it. I've made numerous efforts to find the camera but all with no success. :(

In the meantime I did another test using a simple sheet of paper (0.13mm thick per the digital calipers) cutout as a shim.

The paper shim lifted the IHS off the CPU such that the final stack height was 4.24mm. You'll recall from post #77 that the original stack height was 4.21mm. So at this point the IHS is making a gap to the CPU of 0.09mm versus the original gap of 0.06mm.

Unsurprisingly the temperatures are really bad, worse than stock before delidding when the CPU had a 0.06mm gap and was using the stock TIM.

My observations after having made numerous attempts to shim the IHS off of the CPU is that the CPU temperature is wildly dependent on the gap between the CPU and IHS and it doesn't really matter what TIM I use (I tried IC Diamond as well).

Based on these multiple efforts, my anecdotal conclusion on delidding my 3770k is that the stock CPU TIM that Intel uses is probably just as good as NT-H1 or AS5 in terms of thermal conductivity. I don't believe the stock TIM is the reason Ivy's temps are so high.

I now believe the problem is entirely due to the stock gap that exists between the IHS and the CPU, for my CPU that gap was 0.06mm in stock configuration. Removing the IHS adhesive allowed me to close this gap to basically zero, and for that reason alone my temperatures dropped as dramatically as they did IMO.

I am reluctant to post this because I know it flies in the face of conventional wisdom which is that "Ivy's temps are bad because Intel went and used cheap TIM instead of good quality solder". But based on my efforts and testing to date with my CPU I no longer believe this to be true and I feel I should at least attempt to set the record straight. (but I know I'm gonna be flamed for speaking out about this because it really isn't what folks want to hear)

I am now firmly convinced the sole reason Ivy has elevated temperatures is because of the gap that exists between the CPU and the IHS, a gap that must be filled in with TIM and regardless what TIM I use to fill that gap my temps are horrible unless I take away my shims and let the IHS rest solidly directly on the die itself.

It is not the TIM that is cheap, it is that so much of it is required between the CPU and the IHS in the first place because of the gap.

The only question that remains in my mind is why did Intel leave such a large gap between the IHS and the CPU? Is it for thermal stress cycling reasons? (seems unlikely given that the same CPU's are sold without IHS's for laptops)

The only reason I care to know why Intel left such a large gap under the IHS on the desktop chips is because I don't want to unwittingly destroy my IB from thermal cycling if that is the concern. We'll probably never know the answer.
 

rge2

Member
Apr 3, 2009
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Actually it makes sense that gap plays a major role. Solder has high bulk thermal conductivity (87 w/mk intels indium solder real world measured) and very low contact resistance vs paste. The best paste tested (via dow corning, NREL, other professionals) when applied is never higher than actual measured 3-4 w/mk despite listing of bulk thermals as high as 10 w/mk, because of real world factors, contact, etc.

I earlier thought that intels solder had thinner bondline, but it doesnt, it is thicker per some articles. But lower contact resistance + higher bulk cond, allows gradient to be 1/10 of paste, despite thicker bondline.

Perhaps the space is spec'ed to be used interchangeably with solder or paste. If solder fills that space the gradient will be 1/10 than if filled with paste.

Somewhere I posted the white paper that measured gradient of solder vs paste tim1...posted it on some forum months ago...have to dig that back up.

ok found the pic of table on my pc, but ? how to post pics here....guess I need to relocate the article.

in meantime... the measured thermal resistance of 50 w/mk solder (little less than intels solder this is older specd solder) was .0098 C/W. so 120W loaded cpu gradient would be ~1.1C through the solder joint. This solder joint listed as .005 cm thick. Thermal resistance through silver filled epoxy was measured at .313 C/W and was .0025 cm thick. So for 120W, the temp gradient would be 37C, ie ~37x difference. However this silver filled epoxy is meant for 20W cpus, and has a measured thermal conductance of 0.8 w/mk, roughly 1/4 of todays best measured thermal resistances through pastes of ~ 3w/mk. So looking at about 10C decrease in temps with intels indium solder vs modern paste, given similar bondlines as used.

However, IDC, your testing did answer one question for me. It has been said in some articles that you can use a thin enough bondline with paste to perform close to solder, within a few C according to some, with main difference solder has closer core temp spread in multi core cpus vs paste. And your thicker bondline measurements, shows why intels paste is performing worse than some white papers suggest is possible with thin enough bondline, though very thin bondlines may not be possible when accommodating tolerances of mass production.

They are using thicker bondline typical of solder, but using paste to fill it. As to why, yeah, who knows. There has to be some space to accommodate variance in manufacturing IHS width, attachment of IHS, etc, but no clue as to actual tolerance specs.

ok here is pic, at bottom states the paper it is from...so probably can find it via google dont have time to search now, and it didnt come up right away.
http://imageshack.us/f/411/soldervsdie.jpg/
 
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BonzaiDuck

Lifer
Jun 30, 2004
15,699
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That's interesting, about the bond-line or gap. I might have been the first to say that a thicker layer of TIM (even IC Diamond) would mean an increase of thermal resistance inconsistent with the product's performance in conventional application.

Nemesis_1 says that he ground off the top of the IHS, and I think IDC and I had made a brief discussion about that approach.

As I see it, that sort of effort is a bit over the top in terms of effort for outcome. Also, I thought that IDC had raised the question about whether the heatsink would clear the top of the locking mechanism -- but maybe it does.
 

Idontcare

Elite Member
Oct 10, 1999
21,118
58
91
As I see it, that sort of effort is a bit over the top in terms of effort for outcome. Also, I thought that IDC had raised the question about whether the heatsink would clear the top of the locking mechanism -- but maybe it does.

It won't. The CPU die is ridiculously thin. Really. Even I was a bit taken aback by how thin the die was when I popped off the lid.

If you grind down your IHS such that it is the same height as the CPU then your IHS will be reduced to a metal ring that stands only 140um tall.

To go bare-die direct contact you will have to remove the retention mechanism. I'm not sure if all retention mechanisms are designed the same from mobo to mobo but the one on my MIVE-Z looks to be easily removable with a simple Allen key wrench.

I intend to do this but first I have to get new bolts for my H100 as the standoff height of the H100 bolts are way too high (it would not make contact with the die if I took the IHS out of the picture).