It is really mind blowing, to be frank, that Ivy Bridge is so limited in upper clockspeed. I am referring to the electrical parametrics in this case.
NMOS and PMOS drive currents were substantially improved with 22nm over 32nm, and yet the clockspeed max (fmax) just sucks, didn't move at all.
The lower power consumption is great, that is the benefit of smaller xtors which have less capacitance and the benefit of 3D xtors giving better leakage per micron results. But clockspeed should have improved commensurate with drive currents improving and yet we don't see that in practice
From a device-physics position, I'm at a loss at the moment to satisfactorily explain the clock-limited aspects of my 3770k. I should have realized at least a 10% increase in clocks over my 2600k (5.5GHz operation at same Vcc) and yet that isn't the reality, for anyone.
Since that hasn't happened, it begs the question why Intel bothered to boost their Idrives at all. Ivy Bridge responds as if the 22nm Idrive is no more than that delivered with 32nm.
I have never had trouble understanding this, but maybe while IDC is away, someone can set me straight.
Here's the only graph we have to go on. Bohr 2011 May 3rd, slide 20:
Notice the "22 nm planar" curve (which was so labeled in the previous slide). This curve is sorta parallel to the 32nm planar curve, and there is the implication that the new tri-gate transistors give us a significantly different curve.
This chart shows us "gate delay vs. operating voltage", and it's not a chart I see often. But Intel has given a lot of charts concerning drive current, which you mentioned. Here's Paolo (2005 March 3, slide 36) comparing 65 nm to 95 nm:
Then we have Mistry showing the performance of 45nm (2007 Dec 9, slide 20):
Despite the difference between "I_ON" vs. "I_DSAT", that same data seems to have been used for this stylized version, by Bohr (2008 Oct 20, slide 23):
Then we got 32nm. This is Packan et al. (2009 Dec 11, figure 7):
But there's no drive current data for 22 nm... Intel doesn't want to share it. Instead we have this voltage - vs - speed graph, which is a lot more visceral for overclockers anyway. I have to imagine that the leading "K" CPUs lie on the graph someplace like this:
Overclockers will be pushing the voltage and gate delay down into the lower-right corner, which I've labeled "???" in tribute to the Gnomes of South Park. We don't know what those curves do over there.
I also want to point out the last bit of hard scientific data we ever got on Intel's tri-gate research, Chau et al. (2006 June 13th) where they thoroughly defend the importance of vertical fins:
We all know what happened there.
Chau says that tapered fins give "degraded SCEs". SCE is
Short-channel effect, and if you check that link you'll find links to a bunch of other things that I don't understand, but don't sound too good.
So, my belief is that the lines intersect, and that's why we can't overclock i7-3770K any more than Sandy:
Please fix my drawing. I want to be educated!