David Kanter on Intel's 10 nm plans

[Mondozei]

A long read(for the Twitter age) but well worth it.

http://www.realworldtech.com/intel-10nm-qwfet/

 

[liahos1]

ahh sorry for double posting.

 

[witeken]

I knew it.

http://download.intel.com/newsroom/...esearch_Enabling_Breakthroughs_Technology.pdf

Edit: We saw III-V coming, but how about QWFETs? Thoughts?

 

[Phynaz]

A decade in development.

This stuff is difficult.

 

[NostaSeronx]

SOI at last!

 

[liahos1]

SOI at last!

for the less technically inclined <--- could someone explain what the benefits would be for going to quantum well fets and III-V materials?

Like does this do something better than a normal shrink from 14nm to 10nm using current finfets and silicon

 

[sm625]

A long read(for the Twitter age)

Seriously? It's only a few paragraphs.

 

[William Gaatjes]

Great article, thank you.

 

[witeken]

for the less technically inclined <--- could someone explain what the benefits would be for going to quantum well fets and III-V materials?

Lower power, higher performance.

 

[liahos1]

Lower power, higher performance.

yes understood but is there anyway to quantify a delta between what they would have gotten with a traditional shrink vs quantum fets/III-V. I am assuming not but I am just wondering if that widens the manufacturing performance at this node vis a vis competitors 10nm nodes (already less dense)

 

[Hulk]

The whole article is great but I especially this part:

"Historically, transistor performance (i.e. delay), operating voltage, and transistor current all scaled in tandem with geometry. As a result, the power consumption of a transistor scaled down quadratically, and overall power density stayed constant &#8211; even as the transistor density exploded (courtesy of Moore&#8217;s Law). This phenomenon was codified by Robert Dennard and a team of researchers from IBM in 1975, hence the name &#8211; Dennard scaling."

So in the past power consumption and density scaled equally in a (inverse) quadratic manner so that the net result was no increase in power density but as we know that changed at 22nm with Ivy Bridge. The problem wasn't the total thermal load but rate at which heat could be removed, which was exacerbated by the less than ideal TIM. So my point is that here is some good theory behind why this happened. I'm sure everybody else around here knew this but I didn't.

So is this power density problem going to get better with new techniques for continue to be a problem which will lead to high temps and therefore lower frequency?

 

[Idontcare]

I think this will be true for 7nm, not 10nm.

 

[NTMBK]

I think this will be true for 7nm, not 10nm.

I thought that Intel was going to be jumping to EUV at 7nm? Would it not be quite risky jumping to new materials, new transistor designs, and new lithography all in one go?

 

[Idontcare]

I thought that Intel was going to be jumping to EUV at 7nm? Would it not be quite risky jumping to new materials, new transistor designs, and new lithography all in one go?

No, the materials-based risks are completely orthogonal to the lithography-based risks, that is what the BARC is for (to isolate the optical interactions and make it independent of the underlying substrate).

There are secondary (cross-terms) risks associated with the specific chemical speciation of the BARC/resist stack relative to that of the underlying dielectric stacks when it comes to the plasma etch and ash processes, but that is always the case regardless the choice of litho photons.

The biggest risk, I imagine, is EUV uptime and throughput consistency. Line-down events are nightmarish to a production schedule, creating asystemic costs. The risk of an asystematic cost adder is generally taken to be not worth it if you can otherwise build in a systematic cost adder that is persisting but adds no risk to your production schedule.

 

[witeken]

IDC, do you have anything to say about the Quantum Well FinFETs? I don't know what they are and how they work. Is there a chance Intel will really use those, which would be 2 innovations at once? I thought FinFET had a longer life time.

 

[krumme]

No, the materials-based risks are completely orthogonal to the lithography-based risks, that is what the BARC is for (to isolate the optical interactions and make it independent of the underlying substrate).

There are secondary (cross-terms) risks associated with the specific chemical speciation of the BARC/resist stack relative to that of the underlying dielectric stacks when it comes to the plasma etch and ash processes, but that is always the case regardless the choice of litho photons.

The biggest risk, I imagine, is EUV uptime and throughput consistency. Line-down events are nightmarish to a production schedule, creating asystemic costs. The risk of an asystematic cost adder is generally taken to be not worth it if you can otherwise build in a systematic cost adder that is persisting but adds no risk to your production schedule.

Great post. Looking at the current and near future product portfolio outlook from Intel and eg Samsung how do they then factor asystemic cost different? (/How risk averse they are eg vs new nodes?)

 

[Ajay]

IDC, do you have anything to say about the Quantum Well FinFETs? I don't know what they are and how they work. Is there a chance Intel will really use those, which would be 2 innovations at once? I thought FinFET had a longer life time.

QWFETs and FinFETs are nearly the same thing as far as the gate structure is concerned - so perhaps is part of the reason Mr. Kanter made his prediction.

I favor poster OTIS's predictions on the introduction of Ge/SiGe: http://www.realworldtech.com/forum/?threadid=149685&curpostid=149714

This shifts the risk more toward the manufacture of different structures (GAA), but reduces the risk somewhat on the materials side.

There were some at last years IDF (reading between the lines) that Intel was working on introducing post FinFET structures. It makes me wonder if Intel is doing GAA on 10nm. If that were the case, then what Intel learned @ 14nm, in terms of Lithography, wouldn't translate as directly to a new structure and would easily explain the 10nm delay (of course, so could the introduction of SiGe).

All IMHO.

 

[Arachnotronic]

QWFETs and FinFETs are nearly the same thing as far as the gate structure is concerned - so perhaps is part of the reason Mr. Kanter made his prediction.

I favor poster OTIS's predictions on the introduction of Ge/SiGe: http://www.realworldtech.com/forum/?threadid=149685&curpostid=149714

This shifts the risk more toward the manufacture of different structures (GAA), but reduces the risk somewhat on the materials side.

There were some at last years IDF (reading between the lines) that Intel was working on introducing post FinFET structures. It makes me wonder if Intel is doing GAA on 10nm. If that were the case, then what Intel learned @ 14nm, in terms of Lithography, wouldn't translate as directly to a new structure and would easily explain the 10nm delay (of course, so could the introduction of SiGe).

All IMHO.

If you poke around on LinkedIn, Intel engineers refer to the 10nm node as "10nm FinFET."

 

[Ajay]

If you poke around on LinkedIn, Intel engineers refer to the 10nm node as "10nm FinFET."

Of course, I could easily be wrong. I was reading tea leaves after all. If this is true, then a Ge/SiGe materials solutions seems more likely as it would be very difficult to achieve high enough drive currents otherwise. Also, the quantum mech effects would be getting pretty strong at those feature sizes - no wonder IDC said that the 10nm process is at the hairy edge. Making an even taller, narrower Fin seems pretty nightmarish to me. What it took to achieve a similar feat @ 14nm with a 193 nm light source is way beyond my comprehension - never mind 10nm.

 

[witeken]

III-V at the 5nm seems like a very bad prediction. If you look on page 12, it's basically exactly what Kanter says: http://download.intel.com/newsroom/...esearch_Enabling_Breakthroughs_Technology.pdf. I pointed this out many months ago, but unfortunately I didn't get credited with articles around the internet .

 

[Idontcare]

III-V at the 5nm seems like a very bad prediction. If you look on page 12, it's basically exactly what Kanter says: http://download.intel.com/newsroom/...esearch_Enabling_Breakthroughs_Technology.pdf. I pointed this out many months ago, but unfortunately I didn't get credited with articles around the internet .

Don't take it personal. The only reason Kanter's opinion piece regarding Intel's 10nm is getting the kind of wide-spread exposure it has garnered is because his employer (Linley Group as an analyst and senior editor of the Microprocessor Report) needs to make money and have a return-on-investment (in Kanter that is) by building up his reputation with investors (of Linley Group that is).

Within the analyst community, the Microprocessor Report is well regarded and focused on the same topics by and large.

source: I’m Joining the Microprocessor Report

It does Linley group very little good if it doesn't get Kanter's analyst-impacting op-eds put up in as many places as possible.

Basically it is marketing. Follow the money type stuff.

So don't feel bad or one-upped, you just need a better marketing team pushing your posts for wider-spread exposure and recognition. If that is what you are after. Otherwise take solace in the notion that perhaps it was your posts that motivated Kanter to formulate his op-ed in the first place

 

[witeken]

The smiley was sarcastic.

 

[krumme]

The smiley was sarcastic.

But perhaps follow idc advice non the less

 

[NTMBK]

Don't take it personal. The only reason Kanter's opinion piece regarding Intel's 10nm is getting the kind of wide-spread exposure it has garnered is because his employer (Linley Group as an analyst and senior editor of the Microprocessor Report) needs to make money and have a return-on-investment (in Kanter that is) by building up his reputation with investors (of Linley Group that is).



It does Linley group very little good if it doesn't get Kanter's analyst-impacting op-eds put up in as many places as possible.

Basically it is marketing. Follow the money type stuff.

So don't feel bad or one-upped, you just need a better marketing team pushing your posts for wider-spread exposure and recognition. If that is what you are after. Otherwise take solace in the notion that perhaps it was your posts that motivated Kanter to formulate his op-ed in the first place

To be fair, Kanter was pretty widely quoted and respected on the internet long before he got hired by the MPR.

 

[Idontcare]

To be fair, Kanter was pretty widely quoted and respected on the internet long before he got hired by the MPR.

Oh, absolutely. Didn't mean to imply otherwise. Just saying you are going to see his op-ed pop up in places where it really would have otherwise never appeared (EETimes for example), not by Kanter's doing but by the people who need Kanter writing these things and getting them in from of investors.

From the marketing perspective alone, it is an intriguing sideshow to sit back and watch.

Anyways, we won't know anything official until next year. But I'm guessing if someone had the time and were really inclined to crack this egg they could mine the patent office applications queue and see if there has been a flurry of QWFET patent apps from Intel over the past 12-18 months.