David Kanter on Intel's 10 nm plans

[Fjodor2001]

So how would you guys rate the chance that Kanter's predictions about Intel's 10 nm will come true? 30%, 50, 70%, ...?

 

[Arachnotronic]

Oh, absolutely. Didn't mean to imply otherwise. Just saying you are going to see his op-ed pop up in places where it really would have otherwise never appeared (EETimes for example), not by Kanter's doing but by the people who need Kanter writing these things and getting them in from of investors.

From the marketing perspective alone, it is an intriguing sideshow to sit back and watch.

Anyways, we won't know anything official until next year. But I'm guessing if someone had the time and were really inclined to crack this egg they could mine the patent office applications queue and see if there has been a flurry of QWFET patent apps from Intel over the past 12-18 months.

Check this out...

In 2008, Intel demonstrated for the first time a high-speed, low-power quantum well field effect transistor. The p-channel structure was based on a 40-nm indium antimonide (InSb) material, which was said to achieve a cut-off frequency (fT) of 140-GHz at a supply voltage of 0.5 V.

Transistors made on III-V materials are being explored in research as a means to provide improved performance and low power capabilities beyond what silicon may be able to provide.

In a paper at the International Electron Device Meeting (IEDM) here this week, Intel has taken a step forward with the technology. ''In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-k gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (LSIDE) of 5-nm are reported for the first time,’’ according to the paper.

''The high-k gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5Å with low JG, and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance,’’ according to the paper.

''Compared to the planar high-k InGaAs QWFET with similar TOXE, the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III-V QWFETs for low power logic applications,’’ according to the firm.

http://www.eetimes.com/document.asp?doc_id=1258072

 

[witeken]

Anyways, we won't know anything official until next year.

Where/when would Intel disclose 10nm? Investor Meeting? IEDM? Or only when it launches at Computex '16?

Edit: Concerning the post above me, I wonder what cool stuff Intel is researching at this moment that will go into production over a decade or more.

 

[Arachnotronic]

Where/when would Intel disclose 10nm? Investor Meeting? IEDM? Or only when it launches at Computex '16?

Edit: Concerning the post above me, I wonder what cool stuff Intel is researching at this moment that will go into production over a decade or more.

Notice that Intel will only publish papers disclosing the technologies once the technology has gone into high volume manufacturing.

At that point, Intel gains nothing by keeping the details it publishes secret as competitors could easily tear down production CPU parts and figure out what's up.

 

[witeken]

Notice that Intel will only publish papers disclosing the technologies once the technology has gone into high volume manufacturing.

At that point, Intel gains nothing by keeping the details it publishes secret as competitors could easily tear down production CPU parts and figure out what's up.

When did Intel reveal the 22nm Tri-Gates?

 

[Arachnotronic]

When did Intel reveal the 22nm Tri-Gates?

In May 2011; they went into production in Q4 2011.

 

[Fjodor2001]

Where/when would Intel disclose 10nm? when it launches at Computex '16?

Really, if they're launching Skylake in 2015Q3+?

 

[IntelUser2000]

So in the past power consumption and density scaled equally in a (inverse) quadratic manner so that the net result was no increase in power density but as we know that changed at 22nm with Ivy Bridge.

Sorry to be like this, but this QWFET or whatever is probably just going to continue the trend we had with 22nm and have worse clock speed scaling and thermal issues at the high-end: aka Desktop enthusiast chips

PLENTY of hype that only benefits the Contra-revenue-funded mobile chips. Awesome technology isn't it?

Every gain becomes harder, the gains become less every generation, but marketing hype is at an all time high!

Really, if they're launching Skylake in 2015Q3+?

Yea, why not. "Disclosing" is different from "launch". 10nm is supposedly only little over 1 year from Skylake anyway.

 

[jpiniero]

Where/when would Intel disclose 10nm? Investor Meeting? IEDM? Or only when it launches at Computex '16?

CES 2017 is more like it. I think there's every reason to think they won't talk about it until the very last second.

 

[Ajay]

CES 2017 is more like it. I think there's every reason to think they won't talk about it until the very last second.

Makes sense to me. If the rumors of a Skylake 'refresh' are correct, then we won't see Cannonlake on 10nm till 2017.