[Chipworks] IEDM - Monday was Finfet Day

[kimmel]

http://www.chipworks.com/en/technic...is/resources/blog/iedm-monday-was-finfet-day/

We live in amazing times.

 

[videogames101]

http://www.chipworks.com/en/technic...is/resources/blog/iedm-monday-was-finfet-day/

We live in amazing times.

It's good to step back once and a while and appreciate that! :thumbsup:

 

[Nothingness]

TSMC claims 16FF+ gains 40% speed / 60% power compare to 20nm. I guess that's an 'or' not an 'and'. That nonetheless looks like a good gain (if true of course...).

 

[witeken]

http://www.chipworks.com/en/technic...is/resources/blog/iedm-monday-was-finfet-day/

We live in amazing times.

Some observations.

- TSMC's FinFET is still 1.6x less dense than intel's 'real' 14nm.
- No pictures, lol.

Then, the insane part:

Intel likes to point out their history – this is the second generation finFET, fourth generation HKMG, and sixth generation strained silicon; will their 10-nm be the third, fifth, and seventh generations?

I’m now inclined to think so, since at an Applied Materials event in the evening, when asked about the delay in the 14 nm launch, Mark Bohr was heard to say “We won’t have similar problems at 10 nm”. Mark does not make such comments lightly, so to me that implies two things – the 10-nm process is pretty well locked down already, and it’s unlikely that there are huge structural changes from the 14-nm generation. Indeed, the aggressive shrink from 22 nm to 14 nm puts them well on the way to the predicted 10-nm feature sizes.

I'm getting more and more confidence that Intel will in fact start manufacturing its 10nm chips around the start of 2016, maybe a little earlier if Intel doesn't care about 14nm's short life span as bleeding edge node. Because what higher confidence can you get if Makr Bohr says there will be no such things as this:

All the while, TSMC and Samsung are struggling with yields (~20%) of their 1st gen FinFET (which Intel sold 500M of so far) so expect no significant volume (except Apple, but it might be quite expensive even for them) in 2015. So 10nm could follow really close after what other foundries call 14/16nm, and it will have a 2 node lead (>4 years) with Ge and III-V and will have a significantly lower price per transistor and higher density.

Now Intel has to deliver, but the forecast is astonishing.

Edit: Any PDFs?

 

[TuxDave]

I love it when things in textbooks or academic papers make it to mainstream.

 

[witeken]

I love it when things in textbooks or academic papers make it to mainstream.

I just wished I had more knowledge about these things, but I guess there's no such thing as a free lunch.

What do you think of the comments (like my predictions/observations) you read about things you probably know more of? Are they fun to read?

 

[TuxDave]

I just wished I had more knowledge about these things, but I guess there's no such thing as a free lunch.

What do you think of the comments (like my predictions/observations) you read about things you probably know more of? Are they fun to read?

Predictions and observations are a mix of interesting and frustrating. But since this is just a casual forum, I try to keep the frustration level at a minimum by distancing myself a bit from those types of conversations and moving on when I disagree.

 

[NostaSeronx]

Fd-soi! Fd-soi! Fd-soi!!!!!!!!

Where is it?!

 

[Khato]

Fd-soi! Fd-soi! Fd-soi!!!!!!!!

Where is it?!

The same place that it is in the market? Sorry, too tempting. Will be interesting to see if they come out with anything to counter all the FinFET details coming out though.

 

[Phynaz]

I love it when things in textbooks or academic papers make it to mainstream.

Dave,
Could you please describe what we are seeing in these pix?

 

[AnandThenMan]

Bad dental work? But seriously I have no idea what I'm looking at there...

 

[Phynaz]

EETimes coverage

http://www.eetimes.com/document.asp?doc_id=1325023

 

[NostaSeronx]

Dave,
Could you please describe what we are seeing in these pix?

Anyone can really answer that.

According to ITRS 2011, Cu/Airgap integration is the most promising Cu-Extension technology, as airgap is the ultimate low-k material in microelectronics and air has a lowest dielectric constant close to 1.0.

As it turns out, the source of the signal lag is not so much the metal interconnects themselves but rather the insulation between the wires. So the question of the moment is, what can you put between those wires to prevent the signal from leaking?

Vacuum is the best insulator known. Since the 1990s, many chip manufacturers besides IBM, including Infineon Technologies, in Munich, and STMicroelectronics, in Geneva, have experimented with vacuum cavities, and some have even built prototype chips. But two problems have kept the technology from entering production. A chip needs insulation to shield its wires from one another, but it also depends on that insulation for structural support to survive what can be a rough manufacturing process, as well as the often high temperatures on a printed circuit board. Fill the insulation with holes, and the whole chip might collapse. The second problem is making air gaps compatible with standard chip-fabrication techniques. Despite the performance gains that companies have realized on their test chips with air gaps, added equipment and exotic materials have canceled out the performance gain with a money drain.

http://semimd.com/blog/2014/10/31/air-gaps-in-copper-interconnects-for-logic/

 

[Phynaz]

Anyone can really answer that.

And yet you didn't.

 

[NostaSeronx]

And yet you didn't.

I did. Unfortunately, your eye sight is worse than a bat.

If you want a more simple explanation;
- Peformance-Critical section of BEOL
- Air Gaps used for Low-K

It is so mystical and hard to understand woe is life.

 

[witeken]

Dave,
Could you please describe what we are seeing in these pix?

Bad dental work? But seriously I have no idea what I'm looking at there...

It are the M6-M8 metal layers with air-gaps.

15:40 http://intelstudios.edgesuite.net/im/2014/archive/wh/archive.html

 

[TuxDave]

Dave,
Could you please describe what we are seeing in these pix?

Other answers seem to be good enough but you're looking at wires. The most common industry practice is to have each metal layer exclusively in one direction (aka up and down vs left and right if you're looking down at a die as a 2D drawing). Not sure where this idea first came up but it's works pretty well.

So what you're looking at is a cut through the die which will be perpendicular to some layers (so cutting right through it) and parallel to other layers (so you'll either see a continuous wire or nothing at all depending where you cut). I assume the light is the metal, the dark is the dielectric between the metals and the even darker part the special sauce.

 

[witeken]

An interesting quote from the EE Times article:

And as for yields, the semiconductor industry is unique in that when you throw 20% of your products away you are happy. We have trained ourselves that 80 to 90% is good. But the cost is so high now, we can’t afford to throw so many chips away.

I think that's quite an understatement when I heard people claiming 20nm yields were in the 50% at the beginning of this year and FinFET now are even lower although they initially wanted to start it this quarter or the next one.

 

[liahos1]

An interesting quote from the EE Times article:



I think that's quite an understatement when I heard people claiming 20nm yields were in the 50% at the beginning of this year and FinFET now are even lower although they initially wanted to start it this quarter or the next one.

when people quote yields is there a standardized die size they are using for reference?

 

[Phynaz]

Thanks Dave.

 

[Phynaz]

when people quote yields is there a standardized die size they are using for reference?

Nope.

Functional yields are what most people mean when they say yield. It's just the percentage of functional chips produced.

There's other ways of measuring yield, such as parametric yield - the percentage of chips that meet a certain set of operational parameters.

 

[Arachnotronic]

Really impressive showing from Intel. Tightest gate pitch, tightest metals, and very impressive drive currents.

 

[III-V]

Edit: Any PDFs?

They'll be behind a paywall. But they're not up yet, regardless.

 

[witeken]

I was reading some articles about IEDM at Semiconductor Engineering, and there were some more details:

http://semiengineering.com/unraveling-the-mysteries-at-iedm/

Meanwhile, during a separate panel at IEDM, the focus was on issues at 7nm and beyond. “10nm will be kind of similar to 14nm,” said Karim Arabi, vice president of engineering at Qualcomm. “But at 7nm, we see it as another inflection point.”

In fact, finFET transistors will likely extend to 7nm. But at 7nm or sooner, the industry may need to move towards a new channel material to boost the mobilities. In other words, silicon-based channel materials may simply run out of gas. III-V materials are not ready for 7nm. So, the industry is leaning towards silicon germanium or germanium for the PFET and silicon for the NFET. “Silicon germanium and III-V would be the candidates to consider,” Arabi said. “Silicon germanium is a possibility.”

First of course if the fact that it becomes ever more clear that 7nm is just the foundries' spin of what ought to be called 10nm. Secondly, it seems like the foundries might not use III-V at their 7nm node (aka 10nm), while it's quite clear to me that Intel's focused on III-V:

SE: Some say the III-V materials have been pushed out or delayed. Any thoughts on that?

Bohr: Other companies may choose to push out the adoption of III-V, because all of the problems have not been solved for the 10nm generation. Tool readiness doesn’t seem to be the issue. It’s mostly device physics.

That would give Intel an even greater transistor advantage (3 nodes), and who knows when 5nm (aka 7nm) will even be released? It might be 10 years. Even if Moore's Law dies, I'm sure the PR spin will keep it going for as long as possible! E.g.:

While Intel is ramping up the 14nm technology, TSMC recently accelerated its 16nm finFET production from the fourth quarter of 2015, to the second quarter of next year.

Sounds credible.

 

[Arachnotronic]

Sounds credible.

They'll need to if they're going to supply Apple's A9!