Broadwell core sizes measured

cbn

Lifer
Mar 27, 2009
12,968
220
106
Using the processor die maps shown below and the measurement of 169mm2 for quad core + GT3 found in this document, I came up with these Broadwell core size measurements:

Core M = 6.95 mm2

Dual core GT3 = 6.8 mm2 (without dead space included), 8.5 mm2 (with dead space shown in processor die map included)

Quad core GT3 = 6.85 mm2

(Method of taking measurement: I used the outside edge of the outlines as my starting point. Then I measured the total area for both cores on Core M (and the 2C GT3 die) and then divided by two. For the quad core GT3 die, I measure the total area for all four cores and then divided by four.)







Hopefully we also get a Xeon-D processor die map as I would like to measure those cores as well. However, I feel pretty certain the cores will measure out roughly the same as the ones above.

P.S. The reason I made these measurements was because there was speculation (based on actual statements from Intel) that Core M was using a higher density process than the other Broadwell cores. However, based on the processor core footprint (from these pictures) It doesn't appear to be the case.
 

PaulIntellini

Member
Jun 2, 2015
55
4
41
Changing the layout/size of the core for different market segments would be very time-consuming and costly.

With Haswell, they changed some details of the "process receipes" for the transistor to get a different performance/leake tradeoff:

The 22nm process is optimized for Haswell and includes 11 metal layers (2 additional metal layers vs. Ivy Bridge [2]), high-density metal-insulator-metal (MIM) capacitors, and is tuned for different leakage/speed targets based on the market segment. For example, in some low-power products, the process is optimized to reduce leakage by 75% at Vmin, while paying only 12% intrinsic device degradation at the high-voltage corner.

5.9 Haswell: A family of IA 22nm processors

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6757361

A question for experts:

For the low-power versions, I just had the following idea:

Intel could change the height of the metal stack, reducing the aspect ratio of some of the metal layers. This would reduce capacitance (power) at the expense of higher resistence (lower max frequency).

I wonder if it wold be possible to do and verify this automatically without too much effort?
 
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Enigmoid

Platinum Member
Sep 27, 2012
2,910
31
91
They likely had time to further refine their process. The first 14nm broadwell-U chips do not seem to be performing as well as you would expect. They likely need a new stepping to improve things though this is unlikely as intel will roll out skylake-u relatively soon and broadwell doesn't have much competition.
 

Idontcare

Elite Member
Oct 10, 1999
21,126
12
0
For the low-power versions, I just had the following idea:

Intel could change the height of the metal stack, reducing the aspect ratio of some of the metal layers. This would reduce capacitance (power) at the expense of higher resistence (lower max frequency).

I wonder if it wold be possible to do and verify this automatically without too much effort?
Much easier (less costly and less time required) to adjust the transistor, tailoring its electrical parametrics, than attempting to monkey around with over-polishing the metal stack and risking all the standard dielectric failure and EM issues.
 

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