[Austin Statesman] AMD sees a way forward (with new Zen design)

[stuff_me_good]

blah blah blah

Well said. :thumbsup: Some people just need to learn how to use their brain before womiting bunch of words.

 

[CHADBOGA]

@Boze: This is what I assume about many guys here.

Case of mistaken identity here?

 

[JoeRambo]

Two things to keep in mind when comparing Zen to XV:

1). XV has half the FP execution resources per module compared to Zen's cores:

http://fudzilla.com/news/processors/37639-new-leaked-amd-zen-slide

2). Zen will be moving to an inclusive cache architecture, presumably with much better cache performance than that of XV:

http://www.extremetech.com/gaming/204523-new-leak-hints-at-amd-zens-architecture-organization

Those two changes alone should account for a great deal of the projected 40% improvement in IPC moving from XV to Zen, at least for FP workloads anyway.

This, it is easy to "see a way forward" with Zen given how disastrous BD was. When your baseline is BD (I don't even need to use any words not in forum TOS, BD is synonym), it's hard not to get excited.

Intel's cache are excellent and actually lately they have been giving up quite some latency (probably for power savings), so AMD can catch up a lot just by fixing cache hierarchy. Going inclusive and lowering latencies would work wonders for any task (obviuos, but you tell that to morons who designed BD).
And it's not like Intel has done anything revolutionary, they just have wide OOO CPU with ton of execution resources and amazing instruction latencies/bw. AMD can certainly catch up to most of that by trading extra area and extra power. IF Zen will be performant, nobody will care about extra 20-30% of power if price and TCO is right. For example in mid-entry server market (think about 2S 10 core stuff), AMD can get away with CPU using 30w more on 100% load, as that is maybe 10% of total power more when you account for memory. But you need perf and memory channels to move stuff and to actually show up in a fight (and not with hands smeared in BD).

 

[Dresdenboy]

Case of mistaken identity here?

Yep. Lost the overview on the phone. I corrected it.

 

[DrMrLordX]

These slides are fake and made their rounds earlier this year.

We still don't know much about Zen's FPU.

I thought there were two iterations of those slides, one fake (showing Zen with XV-like FPU) and one not.

Regardless, the only way that Zen could possibly have the same FP restrictions as XV - or any other Construction core - would be to continue the CMT strategy. AMD has declared that they are moving towards SMT, which clearly indicates that each core will have its own dedicated FP resources.

edit: AMD could hit themselves upside the head with a keg o' stupid and restrict themselves to a single 128-bit FMAC per core, but seriously, I don't think they'd do that.

 

[ShintaiDK]

I thought there were two iterations of those slides, one fake (showing Zen with XV-like FPU) and one not.

Regardless, the only way that Zen could possibly have the same FP restrictions as XV - or any other Construction core - would be to continue the CMT strategy. AMD has declared that they are moving towards SMT, which clearly indicates that each core will have its own dedicated FP resources.

edit: AMD could hit themselves upside the head with a keg o' stupid and restrict themselves to a single 128-bit FMAC per core, but seriously, I don't think they'd do that.

Nothing prevents a single FPU design and SMT. But I dont think they will continue that failed path.

You could even run CMT+SMT. Tho I doubt it would be practical.

 

[dark zero]

AMD is not going too far with their failed designs.

Their FPU and the poor RAM bandwidth kills them.

 

[Fjodor2001]

AMD is not going too far with their failed designs.

Their FPU and the poor RAM bandwidth kills them.

Zzzzzz...zzzz...z.z..z.zzz.....

 

[AtenRa]

I read Anandtech since he left Toms, Im a forum member since 2009 and this could be the first time i will use the ignore option.