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News "Aurora’s Troubles Move Frontier into Pole Exascale Position" - HPCwire

moinmoin

moinmoin

Diamond Member
With Sapphire Rapids delayed Intel's Aurora exascale supercomputer misses yet another date. This means Frontier is now on route of becoming the first exascale supercomputer.

www.hpcwire.com

Aurora's Troubles Move Frontier into Pole Exascale Position

Intel’s 7nm node delay has raised questions about the status of the Aurora supercomputer that was scheduled to be stood up at Argonne National Laboratory next year. Aurora was in the running to be the United States’ first exascale supercomputer although it was on a contemporaneous timeline with...
www.hpcwire.com www.hpcwire.com
 
jpiniero said:
This article is dated 8 months ago and Sapphire Rapids isn't on 7 nm.
Click to expand...
Ponte Vecchio is supposed to be on Intel's 7nm. I'll admit that I missed the news last year that Aurora is confirmed to fall back this much.

insidehpc.com

DOE Under Secretary Dabbar's Exascale Update: Frontier to Be First, Aurora to Be Monitored

As Exascale Day (October 18) approaches, U.S. Department of Energy Under Secretary for Science Paul Dabbar has commented on the hottest exascale question of the day: which of the country’s first three systems will be stood up first? In a recent, far-reaching interview with us, Dabbar confirmed...
insidehpc.com insidehpc.com
 
scineram said:
PV is TSMC N6, no? Was that supposed to be fabbed inside originally? When did Intel switch it to external?
Click to expand...
Maybe one can summarize PV as a magical mess? 😉

Raja teased that there are 7 advanced technologies at play here, and by our calculation, these would be:
  • Intel 7nm
  • TSMC 7nm
  • Foveros 3D Packaging
  • EMIB
  • 10nm Enhanced Super Fin
  • Rambo Cache
  • HBM2
Following is how Intel gets to 47 tiles on the Ponte Vecchio chip:
  • 16 Xe HPC (internal/external)
  • 8 Rambo (internal)
  • 2 Xe Base (internal)
  • 11 EMIB (internal)
  • 2 Xe Link (external)
  • 8 HBM (external)
Click to expand...
wccftech.com

Intel Showcases Its Packaging Prowess With 7nm Ponte Vecchio Xe-HPC GPU, Over 100 Billion Transistors & 47 XPU Compute Tiles

Intel has unveiled new details of its 7nm Xe-HPC Ponte Vecchio GPU which is planned to be the largest and most chip designed to date.
wccftech.com wccftech.com
 
jpiniero said:

U.S. Department of Energy’s Argonne National Laboratory and Hewlett Packard Enterprise prepare for exascale era with new testbed supercomputer | Argonne National Laboratory

www.anl.gov www.anl.gov

Argonne has gone ahead and bought a new modest AMD+nVidia cluster. Should be online by early next year. Don't think this means that Aurora is getting cancelled but only because Intel is going to miss the deadline now and will have to give it to them for free (?)
Click to expand...

There s some odd thing here :

Powerful compute to improve modeling, simulation and data-intensive workflows using 560 2nd and 3rd Gen AMD EPYC™ processors
Click to expand...
https://www.amd.com/en/products/epyc
 
jpiniero said:

U.S. Department of Energy’s Argonne National Laboratory and Hewlett Packard Enterprise prepare for exascale era with new testbed supercomputer | Argonne National Laboratory

www.anl.gov www.anl.gov

Argonne has gone ahead and bought a new modest AMD+nVidia cluster. Should be online by early next year. Don't think this means that Aurora is getting cancelled but only because Intel is going to miss the deadline now and will have to give it to them for free (?)
Click to expand...

Intel pre-announced a 300m charge against Q4 earnings, which most people interpret as some penalty payment for missing yet another Aurora deadline.

So, DoE has some pocket change to go on a shopping spree...
 
jpiniero said:
Guess they aren't picky on Rome vs Milan. The focus is really on the GPUs.
Click to expand...

I think the focus is on speed of delivery. Apparently, Intel could not deliver even a modest system using engineering samples to get the programmers start working, so DoE went elswhere, to get the system delivered on (one of the) old Aurora deadline - end of 2021.

This article says that DoE will make a slight upgrade, swapping out Rome for Milan (X?) and the interconnect in March 2022:
Argonne’s 44-Petaflops ‘Polaris’ Supercomputer Will Be Testbed for Aurora, Exascale Era (hpcwire.com)
 
Last edited:
DrMrLordX said:
Ponte Vecchio has chiplets that could wind up being from the following:

Intel 10SFE/Intel7
Intel 7nm/Intel4
TSMC N6
Click to expand...

Compute chiplet is on TSMC N5 and the link tile is on TSMC N7, nothing on Intel 4, at least according to their architecture day presentation.
 
jpiniero said:
^^^ It was originally on Intel 7 nm. Then they said it was a dual source, and now it's just TSMC.
Click to expand...
I have something even better for you. Whenever intel's 7nm progress was doubted, Aurora was the stomping card that to counter any doubts. "They have a contract"

Yeah right... Suppose it served them well, seeing as they will now get a couple of billions of taxpayer dollars as well, just to reassure they have no real obligations to keep government deadlines or tell the truth in quarterly reports.
 
lobz said:
I have something even better for you. Whenever intel's 7nm progress was doubted, Aurora was the stomping card that to counter any doubts. "They have a contract"

Yeah right... Suppose it served them well, seeing as they will now get taxpayer money as well!
Click to expand...

Kind of makes you wonder why they didn't move to TSMC sooner to avoid paying the 300 mill penalty. That 300 mill is likely what's bankrolling this new cluster.
 
jpiniero said:
Kind of makes you wonder why they didn't move to TSMC sooner to avoid paying the 300 mill penalty. That 300 mill is likely what's bankrolling this new cluster.
Click to expand...
Pay a 300 mill fine here, get 20 times as much incentive there 🙂 they know how to play the "free market" game very well 🤣🤣🤣
 
jpiniero said:
That's the crazy thing - how can the Govt trust that Intel's fabs will deliver?
Click to expand...

Intel's fabs are guaranteed to deliver. Other than a few cases like Aurora the government is not looking for leading edge processes, and Intel is not suddenly going to become unable to deliver 14nm or older chips.
 
jpiniero said:
That's the crazy thing - how can the Govt trust that Intel's fabs will deliver?
Click to expand...
I don't think they looks at it that way, during the HotChips33 talks the DoE speaker mentioned the RoI from the Govt point of view is different from the typical companies.
For example during the Bulldozer days, AMD was awarded with Fast Forward 1/2, Path Forward, Design Forward etc. From enthusiast point of view we would have thought it would be crazy to give such contracts to AMD who was failing bad vs Intel, but today AMD (with HPE) looks like they will deliver the first Exascale system for the US.
 
Doug S said:
Intel's fabs are guaranteed to deliver. Other than a few cases like Aurora the government is not looking for leading edge processes, and Intel is not suddenly going to become unable to deliver 14nm or older chips.
Click to expand...

This is totally about leading edge. The article mentions 18A as the Govt's target.
 
jpiniero said:
This is totally about leading edge. The article mentions 18A as the Govt's target.
Click to expand...

That may be their target for another Aurora like supercomputer. The bulk of the chips they buy are far from leading edge. They will buy a tiny fraction of Intel's leading edge output.
 
Doug S said:
That may be their target for another Aurora like supercomputer. The bulk of the chips they buy are far from leading edge. They will buy a tiny fraction of Intel's leading edge output.
Click to expand...

The funding Intel got was intended for theoretical leading edge nodes. There was nothing mentioned about old nodes.
 
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