ATI RV870

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AzN

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To raise performance why else? They sure did raise texture SP ratio on 4670.

RV770 might not have raised SP texture ratio but they sure did raise texture performance by 2.5 folds on same 16ROP.
 

Tempered81

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Jan 29, 2007
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I'm expecting 1.2 times faster performance out of 5870 compared to 4870 - Unless they move to 512bit mem bus.

the shaders i bet move from 800 to 960 per core. And the GDDR5 is a little faster.

 

Janooo

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Aug 22, 2005
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4670 has some other limitations and it's not high end part.
I read somewhere that AMD would like to keep 4:1 ratio.
 

MrSpadge

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Sep 29, 2003
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Didn't bother reading ther translation. But the original article says "at least 1000 SPs", not "1000 SPs"!!

Also interesting:
- they claim half the idle power of former generation (should be 48x0). Sounds good until you consider that going from 38x0 to 48x0 increased idle power by 2 - 3 times, whereas transistor count only increased by <1.5 ..

- mention of a fancy new cooling system, keeping temps in check

- dual die packages in core 2 quad style -> should make building X2s easier as the PCB is not much different from the "normal" one. I don't think they'd go for more than 256 Bit mem bus on such cards though.

MrS
 

AzN

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Originally posted by: Janooo
4670 has some other limitations and it's not high end part.
I read somewhere that AMD would like to keep 4:1 ratio.

What 4670 limitations are you talking about?

Considering a 8 ROP 128bit bus can compete with 3850 16ROP 256bit memory bus I don't see any limitation than massive performance gains.
 

AzN

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Nov 26, 2001
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Originally posted by: jaredpace
I'm expecting 1.2 times faster performance out of 5870 compared to 4870 - Unless they move to 512bit mem bus.

the shaders i bet move from 800 to 960 per core. And the GDDR5 is a little faster.

512bit memory bus would make the chip too big and expensive. If they added 512bit memory controller to a 16ROP it would make the bandwidth useless like 2900xt. This is why I mention 384bit bus with 24ROP's. Somewhere in the middle.

With the added SP and texture units and if they didn't raise SP texture ratio you are right. It will be minor improvements aside of clock speed improvements.

ATI has few choices. One would be going with 384 bit bus with a single powerful GPU other would be keep on improving the 256bit 16ROP's. 2nd choice would be easier on the x2. That's what I think will ATI will do at least this has been the case in the past.

I think ATI should go with both and make 256bit version and 384bit versions honestly. Put where it hurts Nvidia.
 

rjc

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Sep 27, 2007
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Originally posted by: Azn
What are you trying to say? You have changed the subject at hand. First you were talking about how you can change ROP size with gddr3 and gddr5 memory interface now you are speculating that 4870 is tuned for gddr3 when it has GDDR5 memory Interface? :confused:
What i am trying to say is that the memory interface is the defining characteristic, the rop count is just a secondary thing. Years of 16 rops/256bit is an artefact of the gddr3 interface and the speed it runs at. The RV770 memory controller added compatability for gddr5 but does not appear tuned for it as most of the RV770s were still expected to be used with gddr3.

If they gamble and say the RV870 will largely be used with gddr5 then the rops are candidate to be redesigned to handle double the throughput(ie 2x rops or rops that are twice as strong). It depends i guess when the RV870 is expected to debut if its soon then gddr3 will still likely be around, if its late then they have the time to redo the rops.

Sorry for not explaining this well :(

ATI will compensate again by raising Texture count, SP, even ROP. Kind of like what they did with RV770. I don't see what the problem is.
If its at 40nm RV770 the chip with a perfect shrink it will go from ~260mm2 -> 140mm2. Unless packaging improves dramatically that is too small for a 256bit interface let alone a 384 bit one. Maybe if you put 2 together somehow on one die could get it big enough for a 384bit bus....2 billion transistors for sure. Bonus smoke alarm and fire extinguisher with every sale ;)

Here: Nvidia Quadro CX According to specs its 192 shaders and 384 bit bus...not the same proportions as the GTX260(192shaders and 448bit bus). Memory interface is reduced for some reason.

Considering memory controller isn't tied down to SIMD core I don't see what the problem is.
Its a $2000 card with 1.5gb of memory, why would you disable part of the memory interface to slow it down?

The leaked photos of the 55nm GT200 show a chip almost the same size as the G80 which also had a 384bit bus. Isnt it logical that that pad limiting would cause this? Although looking here the R600 was smaller and still managed to fit a 512bit interface somehow.
 

AzN

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Nov 26, 2001
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What i am trying to say is that the memory interface is the defining characteristic, the rop count is just a secondary thing. Years of 16 rops/256bit is an artefact of the gddr3 interface and the speed it runs at. The RV770 memory controller added compatability for gddr5 but does not appear tuned for it as most of the RV770s were still expected to be used with gddr3. If they gamble and say the RV870 will largely be used with gddr5 then the rops are candidate to be redesigned to handle double the throughput(ie 2x rops or rops that are twice as strong). It depends i guess when the RV870 is expected to debut if its soon then gddr3 will still likely be around, if its late then they have the time to redo the rops. Sorry for not explaining this well

ROP is secondary to memory interface? :laugh: Memory bandwidth is useless without ROP. :p

ATI made it compatible for both gddr3 and gddr5. Yes i've read that when there's an error gddr5 interface has to start over but doesn't mean it's fine tuned to be used with gddr3 only. It has a gddr5 memory interface. Perhaps the bandwidth does shrink when there are lot of errors.

Using fine tuned gddr5 memory interface does not mean you can raise ROP count. It is tied to the memory bit bus. I've shown pictures on both Nvidia and ATI cards. This has been continued from past to present. Nothing has changed.


If its at 40nm RV770 the chip with a perfect shrink it will go from ~260mm2 -> 140mm2. Unless packaging improves dramatically that is too small for a 256bit interface let alone a 384 bit one. Maybe if you put 2 together somehow on one die could get it big enough for a 384bit bus....2 billion transistors for sure. Bonus smoke alarm and fire extinguisher with every sale

How are you doing your math? 260mm2 chip becomes 140mm2 because it uses 30% less process? :confused: ATI is going to release the exact same card without more SP texture units to the chip? Why? More room means you can add more SP, TMU to the chip.


Its a $2000 card with 1.5gb of memory, why would you disable part of the memory interface to slow it down? The leaked photos of the 55nm GT200 show a chip almost the same size as the G80 which also had a 384bit bus. Isnt it logical that that pad limiting would cause this? Although looking here the R600 was smaller and still managed to fit a 512bit interface somehow.

Memory bandwidth has very little to do with crunching numbers. It's the SP that is doing all the work with Cuda.

G80 is 480mm. GT200 on a 65nm is 577mm. So a GT200 with 55nm is about the size of G80 which sounds about right with die shrink. Nvidia did not redesign their chip. What Nvidia does is disable memory bus and rop cluster. Pad limiting? Considering 2900xt that has 512bit memory bus was only 420mm in size I don't think it has anything to do with pad limits. I think you've got this pad limiting thing way out of proportion honestly. Too much Tom's hardware can do that to you. :(
 

MrSpadge

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I've shown pictures on both Nvidia and ATI cards. This has been continued from past to present. Nothing has changed.

Such an argument is wrong. Just because it always has been like that doesn't mean it has to be like that. It's likely, but not necessary. Rjc's argument is that 16 ROPs for 256 Bit was just the best balance between performance and cost, considering the data rate of the memory and the chip clock speed. Now that the data rate has almost doubled, but the chip clock stays about the same, they may want to change this balance (or make the ROPs more powerful). I don't know if this is possible though.

260mm2 chip becomes 140mm2 because it uses 30% less process?

55 nm / 40 nm = 0.72. Scaling happens in both lateral directions and since we're interested in the area we have to square this value, giving 0.53. 260 mm^2 * 0.53 = 137.5 mm^2. Clear enough?
(note that this asumes perfect scaling, reality will be a bit worse than that)

ATI is going to release the exact same card without more SP texture units to the chip? Why?

He doesn't say that. It's just an example.

Anyway, the German article says die size will be 205 mm^2, so they do add features. Which should already have been obvious from the claim of DX 11 and >1000 SPs.

Memory bandwidth has very little to do with crunching numbers. It's the SP that is doing all the work with Cuda.

I'm sure he's aware of that. His point is that if people are paying 2000$ for such a card, why shouldn't they get the fully fledged 240 SP / 512 Bit mem configuration?
(Maybe that's available for 3000$ .. ;)

I think you've got this pad limiting thing way out of proportion honestly

Applying it to GT200 with its huge die is certainly out of proportion. But if you wanted to feed a 140 mm^2 GPU with a 386 Bit mem bus you'd get into serious trouble with the pads. These 100 - 150W also have to be delivered in some way.

MrS
 

BFG10K

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Originally posted by: Azn

It's all theoretical even with nvidia's hardware but then when we put it to use with a game it sure doesn't act that way.
Right, so you can?t solely rely on the FLOPs metric to make predictions about the prevalence of shaders in programs. That?s the point.

Unless all the shader games were specifically optimized for ATI SP. We can see many instances where a shader heavy games favor ATI R7XX cards.
Actually the bulk of the heavy lifting is done by the driver compiler, not the game.
 

AzN

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Nov 26, 2001
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Such an argument is wrong. Just because it always has been like that doesn't mean it has to be like that. It's likely, but not necessary. Rjc's argument is that 16 ROPs for 256 Bit was just the best balance between performance and cost, considering the data rate of the memory and the chip clock speed. Now that the data rate has almost doubled, but the chip clock stays about the same, they may want to change this balance (or make the ROPs more powerful). I don't know if this is possible though.

Unless there's evidence ROP to memory bit bus has changed we can only assume it will be same. RJC says gddr5 can use 32ROPs while gddr3 16ROP is quite wrong.

55 nm / 40 nm = 0.72. Scaling happens in both lateral directions and since we're interested in the area we have to square this value, giving 0.53. 260 mm^2 * 0.53 = 137.5 mm^2. Clear enough? (note that this asumes perfect scaling, reality will be a bit worse than that)

Are you sure you are doing you math right? How are you getting this .53 from?

What is the size of G92B chips that is on 55nm? 270mm2

What about G92A that is on 65nm? 330mm2

Exact same chip how come it didn't scale like your math did? :brokenheart:


He doesn't say that. It's just an example. Anyway, the German article says die size will be 205 mm^2, so they do add features. Which should already have been obvious from the claim of DX 11 and >1000 SP

Of course he said that. He's saying ATI needs to sell smoke alarms and fire extinguisher with every single card because some how ATI is going to sell pad limited chips.

I'm sure he's aware of that. His point is that if people are paying 2000$ for such a card, why shouldn't they get the fully fledged 240 SP / 512 Bit mem configuration? (Maybe that's available for 3000$ ..

You should have paid attention. He was specifically asking how memory bit bus shrunk while SP did not going back to his pad limit assumptions with GT200 on 55nm.


Applying it to GT200 with its huge die is certainly out of proportion. But if you wanted to feed a 140 mm^2 GPU with a 386 Bit mem bus you'd get into serious trouble with the pads. These 100 - 150W also have to be delivered in some way.

Why are you applying 140mm chip with a 384 bit memory bus? Baseless assumptions on your part as well. ATI is somehow going to shrink RV770 and stick 384bit bus? Was I even saying that in the first place? Yeah really... :roll:
 

AzN

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Originally posted by: BFG10K


Unless all the shader games were specifically optimized for ATI SP. We can see many instances where a shader heavy games favor ATI R7XX cards.
Actually the bulk of the heavy lifting is done by the driver compiler, not the game.

That's what I said in previous posts a while back. I don't remember which thread. :)

Right, so you can?t solely rely on the FLOPs metric to make predictions about the prevalence of shaders in programs. That?s the point.

I've also said shader wasn't necessarily the driving force in games either.
 

Karathkasun

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Oct 28, 2008
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Sorry to mention to the people claiming rop/mem bus ratio...

The rop/mem bus ratio only really applied to G80. If they were directly tied together on Ati chips, r600 would have had 32 rops.
Not to mention the r600 GT, which should have only had 8 by that same rule you claim is true. (it actually has 12, Ive checked.)

The memory bus is only decided by how many bits (pads) are available on the chip to connect
to memory, and how many are actually connected to something. (On Ati cards at least)

The G80's memory controller was closely tied to the ROP units, as each ROP had a 16 bit path
directly to the memory. (24 rops X 16 bits = 384 bit bus or 20 X 16 = 320)



edit: oops, missed the diagram, I'm still not sure about that though. Those diagrams tend to
be way over simplified.
 

Karathkasun

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Oct 28, 2008
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Your post prior being edited was incorrect, r600 does not have a 2 ROP per 64 bits of memory BW (nor does the rv670 have a 4ROP to 64bit ratio) as you previously stated.

r600gt (same chip as r600 but with 1 rop cluster cut thus 12 rops) has a 256 bit bus, not to mention r600pro (all 16 ROPs but some had 256 bit bus) By your logic they should only have 8 rops.

The 256 bit bus was achieved simply by wiring the pcb differently or in the case of the gt/pro256b, omitting 1/2 of the dram chips. (the pro256b uses chips that are twice as dense thus getting 512mb with 1/2 the chips)

Think back to the 1950GT same exact chip as 1950/xt/xtx but had a laser cut on the die to disable one ROP quad, same goes for x800 and x800xl/xt or x850 and x850xt.

The ROPs are not tied to memory except on G80 and possibly some newer ATI cards.

You are just attaching an arbitrary ratio to these things and claiming your ratios are set in stone. The architectures do not work that way.

On Ati cards (up to rv670 that I know of), everything is connected to a central crossbar or ring bus. This includes the memory controllers.

In this setup you can change the ratios on a whim by disabling silicon on low yield parts or spinning a slightly different chip like r520 -> r580.

The G80 was the only card I absolutely know of that the ROPs had the memory read/write circuit
combined with them as would lead to a ROP/memory interface ratio as you talk about.

AFAIK the G92/GT200 do not work this way anymore anyway, so the G80's memory management was an anomaly in the way things work with graphics cards.

EDIT: As a matter of fact, I KNOW G92 does not work the way you say. There was a limited run on 9600gso's that could be flashed to 8800gt's. the bios on the card only deactivated one of the memory channels making the card 192bit. After the flash you would have 256bit memory but still the same amount of shaders and rops. Someone else correct me if Im wrong.

EDIT: EDIT: notice the post edits changing your tune, Ive proved my point. peace out.
 

AzN

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Nov 26, 2001
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It was called RV570 first of all. basically a cut version of Rv580. Back then ATI was using Internal Ring Bus Architecture which might not have been tied to ROP. I couldn't find a diagram on the web.

RV770 uses hub architecture. very similar to Nvidia's cards which are tied to ROP.

FYI g92 and Gt200 memory controllers are also tied to ROP.

EDIT: As a matter of fact, I KNOW G92 does not work the way you say. There was a limited run on 9600gso's that could be flashed to 8800gt's. the bios on the card only deactivated one of the memory channels making the card 192bit. After the flash you would have 256bit memory but still the same amount of shaders and rops. Someone else correct me if Im wrong.

No. flashable GSO were turned into full fledged g92GTS.
 

Cookie Monster

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I dont think nVIDIA chips use any sort of hub architecture.

Plus i dont think the ROPs are tied to the memory controllers either on the RV770.
 

Cookie Monster

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May 7, 2005
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Guess they do.

Hopefully AMD will have "true" angle-independent AF for the RV870, something similiar or better to the current AF algorithm used by nVIDIA.
 

rjc

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Sep 27, 2007
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Originally posted by: Azn
Using fine tuned gddr5 memory interface does not mean you can raise ROP count. It is tied to the memory bit bus. I've shown pictures on both Nvidia and ATI cards. This has been continued from past to present. Nothing has changed.

Ok, working quickly from from the wikipedia page for memory bandwidth:
RV670
3850 GDDR3 53
3870 GDDR3 57.6
3870 GDDR4 72
RV770 (which had ROPs with doubled power according to Rage3d)
4830 GDDR3 57.6
4850 GDDR3 63.6
4870 GDDR5 115.2
According to Nordic Hardware
RV870 GDDR5 up to 150

Surely if the new card goes with this memory they will have to increase the ROPs again or they will lose the balance the RV770 had and end up with a similar situation to the RV670?

They only things i can see stopping them is lack of time, the possibly they will still want to run the RV870 on GDDR3 or finally something in dx11 that changes things.

How are you doing your math? 260mm2 chip becomes 140mm2 because it uses 30% less process? :confused: ATI is going to release the exact same card without more SP texture units to the chip? Why? More room means you can add more SP, TMU to the chip.

260mm2 x (40/55)^2 ~ 140mm2

Apparently according to current rumors the first chip on 40nm for ATI will be a die shrunk RV770 which cause of the size will have a 128bit bus on GDDR5. The idea is to replace to 4850 in the lineup with this, the smaller chip + cheaper board offsetting the GDDR5 cost. After follows the RV870 with extra stuff to fill it up to be big enough for 256 bit memory interface.

G80 is 480mm. GT200 on a 65nm is 577mm. So a GT200 with 55nm is about the size of G80 which sounds about right with die shrink. Nvidia did not redesign their chip. What Nvidia does is disable memory bus and rop cluster.

Maybe, they did cut the memory interface when they went from G80->G92 and the GT200 is not selling at the same $ it was introduced at so they would want to be saving money wherever possible.

Pad limiting? Considering 2900xt that has 512bit memory bus was only 420mm in size I don't think it has anything to do with pad limits. I think you've got this pad limiting thing way out of proportion honestly. Too much Tom's hardware can do that to you. :(

There are a lot more constraints now though: the GDDR5 interface requires 34 pins over GDDR3, the sideport thingy + extra power and ground pins. And most importantly people dont look like they would be willing to pay enough $ for another R600 style chip at the moment.

Here's a beyond3d thread for consideration.

 

AzN

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Nov 26, 2001
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Originally posted by: rjc
Originally posted by: Azn
Using fine tuned gddr5 memory interface does not mean you can raise ROP count. It is tied to the memory bit bus. I've shown pictures on both Nvidia and ATI cards. This has been continued from past to present. Nothing has changed.

Ok, working quickly from from the wikipedia page for memory bandwidth:
RV670
3850 GDDR3 53
3870 GDDR3 57.6
3870 GDDR4 72
RV770 (which had ROPs with doubled power according to Rage3d)
4830 GDDR3 57.6
4850 GDDR3 63.6
4870 GDDR5 115.2
According to Nordic Hardware
RV870 GDDR5 up to 150

Surely if the new card goes with this memory they will have to increase the ROPs again or they will lose the balance the RV770 had and end up with a similar situation to the RV670?

They only things i can see stopping them is lack of time, the possibly they will still want to run the RV870 on GDDR3 or finally something in dx11 that changes things.

So what does that have to do with your original statement about GDDR5 can use 32ROP while GDDR3 can not?

Considering RV770 ROP is tied to memory bus I don't see how they are going to raise the ROP without raising the memory bit bus unless they went back to their original ring bus method which was a power hog with higher latencies. I don't think ATI is going to do that.

If these early rumors are true which I highly doubt it seems ATI is aiming for a 256bit bus with faster GDDR5 memory. They can maybe have 32ROP's. Say 8 ROP for every 64bit memory controller which it won't matter if they used gddr3 or 5. That would make the chip 2x larger than what the RV770 is now so that's probably out of the question.

How are you doing your math? 260mm2 chip becomes 140mm2 because it uses 30% less process? :confused: ATI is going to release the exact same card without more SP texture units to the chip? Why? More room means you can add more SP, TMU to the chip.

260mm2 x (40/55)^2 ~ 140mm2

Apparently according to current rumors the first chip on 40nm for ATI will be a die shrunk RV770 which cause of the size will have a 128bit bus on GDDR5. The idea is to replace to 4850 in the lineup with this, the smaller chip + cheaper board offsetting the GDDR5 cost. After follows the RV870 with extra stuff to fill it up to be big enough for 256 bit memory interface.


How do you figure? I get 190mm2

Wow you got all that after reading nordic who quote that unreliable german site? 128bit bus gddr5? That makes no sense. Why would they lower specs? They want faster performance not slower.


G80 is 480mm. GT200 on a 65nm is 577mm. So a GT200 with 55nm is about the size of G80 which sounds about right with die shrink. Nvidia did not redesign their chip. What Nvidia does is disable memory bus and rop cluster.

Maybe, they did cut the memory interface when they went from G80->G92 and the GT200 is not selling at the same $ it was introduced at so they would want to be saving money wherever possible.

No the chip is for cuda. Crunching numbers. memory bandwidth or ROP has nothing to do with crunching numbers. It's the SP that does all the work.


Pad limiting? Considering 2900xt that has 512bit memory bus was only 420mm in size I don't think it has anything to do with pad limits. I think you've got this pad limiting thing way out of proportion honestly. Too much Tom's hardware can do that to you. :(

There are a lot more constraints now though: the GDDR5 interface requires 34 pins over GDDR3, the sideport thingy + extra power and ground pins. And most importantly people dont look like they would be willing to pay enough $ for another R600 style chip at the moment.

Here's a beyond3d thread for consideration.

What does people not wanting R600 chip style have anything to do with RV770 style chips with higher ROP, higher SP texture ratio, more SP, and wider memory bus?

R600 was a mistake on ATI's part because it just didn't have the fillrate to take advantage of that 512bit ring bus. Lot of that bandwidth was wasted which ATI fixed with RV670.

You link me to a beyond forum which they talk about 384bit bus being a viable option with only 300mm die size which you were quoting 400mm in your very first reply. With a die shrink, 24ROP, 96TMU, 1280SP, on a 384 bit bus with high speed gddr5 isn't out of the question. If the die size is too small they can easily add more SP and texture units to compensate just like they did with RV770.
 

MrSpadge

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Sep 29, 2003
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Azn,

do you know the difference between a and a^2? Do you know how to calculate the area of a rectangle and a square?
I'll write a proper answer in the evening.

CU,
MrS
 

AzN

Banned
Nov 26, 2001
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MrSpadge,

Square root 2 is 4. Square root of 4 is 16. Does that answer your question?

Perhaps your formula if off.

You still haven't answered my previous question.

G92A=330mm2 65nm
G92B=270mm2 55nm

Exact same chip how come it didn't scale like your math did?


edit:
Here's a picture of the chips.

http://i114.photobucket.com/al...3/Wirmish/GPU-Dies.png
 

MrSpadge

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Back again.. pretty tired, but there should be enough time left for a reply.

The scaling:
Features like transistors are placed on a die in a single plain (don't bother with hight and interconnects for now). That means e.g. a transistor occupies an area A defined by a certain length l and a width w. Primary school tells us that A = l * w. So if your typical feature is reduced from 55 to 40 nm you have to apply the scaling to both, l and w. Now A = (40/55)*l * (40/55)*w = (40/55)^2 *l*w. 40/55 = 0.72 and 0.72*0.72 = 0.53. 260 mm^2 * 0.53 = 137 mm^2. You see, there's not much room for any mistakes in these simple steps. Is it clear where this comes from?

Regarding your very valid question: note that I put in brackets "note that this assumes perfect scaling, reality will be a bit worse than that". Not all elements on a chip can be scaled down the same way as transistors and I'm not 100% sure if transistors always get the full size reduction in both dimensions. These factors depend on the details of the actual physical implementation. Additionally in cases of "a dumb optical shrink", where you don't redesign your chip, you might get wasted space between functional blocks. You have to rearrange the blocks to optimize space usage, but then you'd have to redo all the timings, thus negating the advantage of the "simplicity" of a pure optical shrink.

Let's take a look at another example: Athlon 64 going from 130 nm Newcastle (144 mm²) to 90 nm Venice (83.5 mm²). According to your method you'd get 90/130 * 144 = 99.6 mm². Theoretically it should be (90/130)² * 144 = 69 mm². So going with the square of the "smallest feature size" (the xx nm number) and allowing for some inefficiency is a good rule of thumb and may underestimate the size after the die shrink, whereas just going with the feature size overestimates the size and is thus wrong. In the first case it's not the formula / maths which is wrong, it's just that we don't know the exact efficiency.

And something else to note: 40, 55, 80, 110 and 150 nm are "half node" processes, which, if I remember correctly, means that not all features are scaled down from the corresponding normal / "full node" processes (45, 65, 90, 130 and 180 nm).

MrS
 

MarcVenice

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I hope it DOES get taped out soon, I'm DIEING to upgrade and this could be the thing I've been waiting for ...