Question [AT]Cannon Lake deep dive review

[NTMBK]

Ian managed to get his hands on a processor that Intel definitely didn't want him to have. It's fascinating- there's a few corner cases where it beats out Kaby Lake, but in general it loses to the 14nm predecessor. The AVX-512 functionality looks really nice, but the clocks just aren't there. You can see why Intel quietly killed this thing off.

https://www.anandtech.com/show/13405/intel-10nm-cannon-lake-and-core-i3-8121u-deep-dive-review

 

[StrangerGuy]

It's almost comical how Intel's tunnel-visioned itself on a questionable quest for process leadership while ignoring uarch design and ending up getting nothing to show for.

 

[ZGR]

The AVX 512 performance is pretty cool though for such a low powered chip.

Any modern CPU could be inside this laptop it would provide a horrible user experience. I'm more embarrassed for Lenovo than Intel.

Glad Ian did get the opportunity to review this mysterious chip.

I can see this laptop being a collectors item for someone who wants to own this rare chip.

 

[Insert_Nickname]

The AVX-512 functionality looks really nice, but the clocks just aren't there. You can see why Intel quietly killed this thing off.

The AVX 512 performance is pretty cool though for such a low powered chip.

I wouldn't be surprised if getting AVX-512 frequency to a reasonable range are an issue. On one 1.8GHz doesn't sound impressive, but **** the performance to show from it is impressive.

I think the biggest issue with the design is the IGP. Intel just wasn't able to get it working in the required time frame. If you've noticed, they have dropped Gen10 quietly, and jumped straight to Gen11. (Pun might or might not be intended)

Glad Ian did get the opportunity to review this mysterious chip.

I can see this laptop being a collectors item for someone who wants to own this rare chip.

Definitely to both.

Cannonlake Collectors Edition anyone?

 

[jpiniero]

I think the biggest issue with the design is the IGP. Intel just wasn't able to get it working in the required time frame. If you've noticed, they have dropped Gen10 quietly, and jumped straight to Gen11. (Pun might or might not be intended)

It was a yield issue and not actually anything wrong with the IGP. Intel I'm sure had plans to release a Cannonlake model with the IGP enabled if yields improved much, but since they didn't in time they threw together the 8130U.

Note that in Gen11 Intel seems to have made changes so individual EUs can be disabled for yield purposes; before that it looks like the IGP was a all or nothing deal.

 

[Thala]

Using ARM64 version of POV-Ray for Windows i am getting a benchmark score of 825 on my Snapdragon 835 (Cortex A53/73) based device - essentially matching the 15W Intel CPUs with active cooling. Now i am sure that the 4 core Intel CPUs pulling ahead - but again we are talking <5W TDP here.

Disclaimer: Unfortunately i had to use the standard C code path without any NEON when compiling for ARM64 - otherwise the score might have been higher. For x64 CPUs POV-Ray has an AVX2 code-path.

 

[Tup3x]

Using ARM64 version of POV-Ray for Windows i am getting a benchmark score of 825 on my Snapdragon 835 (Cortex A53/73) based device - essentially matching the 15W Intel CPUs with active cooling. Now i am sure that the 4 core Intel CPUs pulling ahead - but again we are talking <5W TDP here.

Disclaimer: Unfortunately i had to use the standard C code path without any NEON when compiling for ARM64 - otherwise the score might have been higher. For x64 CPUs POV-Ray has an AVX2 code-path.

Makes me wonder if ARM based SoCs will soon be a real threath for Intel in laptops.

 

[rainy]

I think, that most amazing part of this review is how dishonest was Intel about 10nm issues.

 

[Insert_Nickname]

It was a yield issue and not actually anything wrong with the IGP. Intel I'm sure had plans to release a Cannonlake model with the IGP enabled if yields improved much, but since they didn't in time they threw together the 8130U.

I'm not disagreeing. The design itself might have been sound and working. But if you can't get it to yield, then it's back to the proverbial drawing board anyway.

Note that in Gen11 Intel seems to have made changes so individual EUs can be disabled for yield purposes; before that it looks like the IGP was a all or nothing deal.

Seems like a sound way forward with the issues they've been having. I actually thought Gen9(.5) had some capability for this already. Remember those odd 23EU i3's?

 

[Elfear]

Excellent article by Ian. These are the types of deep-dive articles that made me come to Anandtech in the first place.

 

[Brunnis]

Good, meaty article. Unusually large number of small grammatical errors or odd wordings, though. Regarding CNL, it provides a disappointingly small IPC improvement. I was hoping for something more like IVB, but that certainly doesn’t appear to be the case.

Using ARM64 version of POV-Ray for Windows i am getting a benchmark score of 825 on my Snapdragon 835 (Cortex A53/73) based device - essentially matching the 15W Intel CPUs with active cooling. Now i am sure that the 4 core Intel CPUs pulling ahead - but again we are talking <5W TDP here.

Disclaimer: Unfortunately i had to use the standard C code path without any NEON when compiling for ARM64 - otherwise the score might have been higher. For x64 CPUs POV-Ray has an AVX2 code-path.

For comparison, a 10W 4-core Pentium J5005 scores 697 in the POV-Ray bench. That’s also without AVX (since the chip doesn’t have it). See here:

https://forums.anandtech.com/threads/the-intel-atom-thread.2341969/post-39402293

 

[insertcarehere]

The spec2006 results are telling:

Cannonlake @2.2ghz/SD 855 (A76) @2.8ghz:
400.perlbench: 24.8/26.89
401.bzip2: 16.6/21.66
403.gcc: 27.6/27.65
429.mcf: 25.9/19.15
445.gobmk: 19.0/24.62
456.hmmr: 23.5/32.54
458.sjeng: 22.2/21.81
462.libquantum: 70.5/70.45
464.h264ref: 39.7/46.89
471.omnetpp: 17.5/15.6
473.astar: 14.2/17.55
483.xalancbmk: 27.1/28.73
433.milc: 24.6/25.27
444.namd: 23.0/28.73
450.soplex: 39.1/37.1
453.povray: 34.1/41.06
470.lbm: 59.9/44.04
482.sphinx3: 43.2/39.64

ARM has basically caught up to Intel (and by extension AMD) in the mobile space.

 

[scannall]

The spec2006 results are telling:

Cannonlake @2.2ghz/SD 855 (A76) @2.8ghz:
400.perlbench: 24.8/26.89
401.bzip2: 16.6/21.66
403.gcc: 27.6/27.65
429.mcf: 25.9/19.15
445.gobmk: 19.0/24.62
456.hmmr: 23.5/32.54
458.sjeng: 22.2/21.81
462.libquantum: 70.5/70.45
464.h264ref: 39.7/46.89
471.omnetpp: 17.5/15.6
473.astar: 14.2/17.55
483.xalancbmk: 27.1/28.73
433.milc: 24.6/25.27
444.namd: 23.0/28.73
450.soplex: 39.1/37.1
453.povray: 34.1/41.06
470.lbm: 59.9/44.04
482.sphinx3: 43.2/39.64

ARM has basically caught up to Intel (and by extension AMD) in the mobile space.

If you add Apple to that list, it shows there is a lot of grunt left in ARM.

Cannonlake @2.2ghz/SD 855 (A76) @2.8ghz Apple A12 2.5 Ghz
400.perlbench: 24.8/26.89/45.3
401.bzip2: 16.6/21.66/28.5
403.gcc: 27.6/27.65/44.6
429.mcf: 25.9/19.15/49.9
445.gobmk: 19.0/24.62/38.5
456.hmmr: 23.5/32.54/44.0
458.sjeng: 22.2/21.81/36.6
462.libquantum: 70.5/70.45/113
464.h264ref: 39.7/46.89/66.59
471.omnetpp: 17.5/15.6/35.73
473.astar: 14.2/17.55/27.25
483.xalancbmk: 27.1/28.73/57

 

[LTC8K6]

Is this the original 10nm chip type that Intel demoed in January of 2017 at CES?

I guess there's no way to know.

 

[Hi-Fi Man]

Aren't these benches largely multi-thread friendly? If so, then it's kind of inaccurate to say "ARM has caught up" and before any one says "well the TDP is lower!" the thing is; an i3 or what have you is built to perform well in what one could argue is a much larger set of tasks. As a result, power consumption may be higher, but a big core Intel CPU is going to provide more balanced performance and a better overall desktop experience than say a Snapdragon 835. All this without even going into how comparing TDP between different CPUs let alone manufacturers is pointless.

TLDR: Don't jump the gun. CISC isn't going anywhere yet especially when these ARM CPUs don't have a large performance lead like Alpha and such did in the 90s.

 

[naukkis]

TLDR: Don't jump the gun. CISC isn't going anywhere yet especially when these ARM CPUs don't have a large performance lead like Alpha and such did in the 90s.

But they do. Especially performance/watt.

 

[Hi-Fi Man]

But they do. Especially performance/watt.

I beg to differ. Perhaps performance per watt (debatable) but not performance. A Snapdragon 835 is not going to out perform an i3 8121U in single threaded tasks, and just look at the AVX512 numbers...

 

[NTMBK]

I beg to differ. Perhaps performance per watt (debatable) but not performance. A Snapdragon 835 is not going to out perform an i3 8121U in single threaded tasks, and just look at the AVX512 numbers...

Sure, but 512 bit vectors are pretty huge. How many problems are amenable to AVX-512 that aren't also a good fit for GPUs?

 

[Insert_Nickname]

The 80's called. They want their RISC vs CISC discussion back.

No, seriously. This has been debated backwards, forwards, up, down and sideways for the last 30 years. Both have advantages and disadvantages. Most don't even realise that modern x86(_64) CPUs are essentially RISC inside.

 

[BigDaveX]

I can see ARM probably taking over as the architecture of choice for Chromebooks and the like at some point, but I really don't see x86 going anywhere on the home computing front anytime soon. The amount of effort required to shift any significant portion of the industry over to ARM would make Apple's transition from PowerPC to x86 back in the mid-2000s seem like a cakewalk in comparison.

 

[Thala]

I beg to differ. Perhaps performance per watt (debatable) but not performance. A Snapdragon 835 is not going to out perform an i3 8121U in single threaded tasks, and just look at the AVX512 numbers...

Performance/Watt is what really matters. If you have more power headroom you can design bigger cores. Design point for Cortex A76 is still 750mW/core while matching IPC of Kabylake/Skylake cores.
The number i posted above are from almost 3 year old Cortex A73 - just out of curiosity how it compares to the 10nm 15WTDP i3 8121U.

Most don't even realise that modern x86(_64) CPUs are essentially RISC inside

If i want to design a RISC core - a would design a RISC core and not a RISC core with some CISC shell with microcode around it just to suck up power. I also would employ a weakly ordered memory model - like any modern architecture except x86/x64 of course. In addition i would expose at least 32 architectural registers and not only 16 like in x64. The only thing keeping x86/x64 afloat is the ecosystem - but thats another topic i guess.

 

[Arachnotronic]

Sure, but 512 bit vectors are pretty huge. How many problems are amenable to AVX-512 that aren't also a good fit for GPUs?

The benefit to AVX-512 is that it's right there on the CPU. If you're a data center and you're going to buy a bunch of CPUs, it's really nice to have that capability right there in the silicon you're already buying. Don't dismiss that advantage over GPGPU.

 

[insertcarehere]

Aren't these benches largely multi-thread friendly? If so, then it's kind of inaccurate to say "ARM has caught up" and before any one says "well the TDP is lower!" the thing is; an i3 or what have you is built to perform well in what one could argue is a much larger set of tasks. As a result, power consumption may be higher, but a big core Intel CPU is going to provide more balanced performance and a better overall desktop experience than say a Snapdragon 835. All this without even going into how comparing TDP between different CPUs let alone manufacturers is pointless.

TLDR: Don't jump the gun. CISC isn't going anywhere yet especially when these ARM CPUs don't have a large performance lead like Alpha and such did in the 90s.

Spec2006 is pretty explicitly a single core benchmark.

 

[SarahKerrigan]

If i want to design a RISC core - a would design a RISC core and not a RISC core with some CISC shell with microcode around it just to suck up power. I also would employ a weakly ordered memory model - like any modern architecture except x86/x64 of course. In addition i would expose at least 32 architectural registers and not only 16 like in x64. The only thing keeping x86/x64 afloat is the ecosystem - but thats another topic i guess.

Most x86 ops don't touch the microcode engine (only ops that translate to greater than four uops, AFAIK) - and microcode is far from exclusive to CISC designs.

 

[beginner99]

The benefit to AVX-512 is that it's right there on the CPU. If you're a data center and you're going to buy a bunch of CPUs, it's really nice to have that capability right there in the silicon you're already buying. Don't dismiss that advantage over GPGPU.

While I agree that it can be a huge advanatge and a skyklake server CPu can beat in GV100 in some scenarios at inferencing BUT only with the exactly right software and config which is the real issue here, the software. It just isn't that straight forward as often default builds of tools aren't even compiled for AVX. So you need to first check that and then compile yourself (good luck with that if you aren't on linux).