[AT] AMD Reorganizes Business Units - no more high performance x86 cores?

[pTmdfx]

It's a bit early to start declaring frequency targets, given that we know almost nothing about it 😵

Yah, too early. But I would wipe high 3 Ghz away for ARM K12 at the beginning, given how I expect the server market shapes & what AMD's ARM solutions are targeting in 2016. I have limited insight, tho.
😵

 

[Homeles]

For a moment i thought you were describing Intel's graphics and tablet financials, next year will be the next big thing that never comes 🙄

Can't wait to quote you on this next year.

It looks like we're getting a group deal on that vacation. You can join AtenRa and Intel17 on their little adventure.
-ViRGE

 

[krumme]

WAG: Lisa was probably offered CEO position somewhere else so they had to promote her to COO with promise to CEO soon...which is very good news for AMD.

She sure looks like the brain for what have happened the last years. But its difficult to know from the outside, but she sounds very well informed and balanced.

AMD have never been so well managed as it is now, - not by a long stretch - shown imho with the competitive strenght/weakness of the portfolio vs profit. Whatever happens she is in for a major position.

 

[pTmdfx]

WAG: Lisa was probably offered CEO position somewhere else so they had to promote her to COO with promise to CEO soon...which is very good news for AMD.

She was the SVP & GM of "Global Business Units", which... sounds just a COO position without the title. Note that each business unit has its own CVP & GM under this SVP position.

 

[Fjodor2001]

Lots of off topic stuff in this thread lately.

An attempt to bring it on topic: How do you think AMD's new non-Bulldozer-based x86 uArch fits into the strategy presented by AMD in the article linked to from the OP?

They already have a quite new uArch for the low end/mobile stuff, so where does this new x86 uArch fit in? Sounds to me it's targeting the higher end desktop/server segment. But doesn't that contradict what's started in the article, where they say they'll be focusing on perf/power and not top end performance? 😕

 

[Phynaz]

Lots of off topic stuff in this thread lately.

An attempt to bring it on topic: How do you think AMD's new non-Bulldozer-based x86 uArch fits into the strategy presented by AMD in the article linked to from the OP?

They already have a quite new uArch for the low end/mobile stuff, so where does this new x86 uArch fit in? Sounds to me it's targeting the higher end desktop/server segment. But doesn't that contradict what's started in the article, where they say they'll be focusing on perf/power and not top end performance? 😕

First you need AMD to define their meaning of "High Performance".

Then you need to understand that high performance does not mean top end performance.

 

[Fjodor2001]

First you for AMD to define their meaning of "High Performance".

Then you need to understand that high performance does not mean top end performance.

I think it's clear what we're talking about - replacements for the Bulldozer-based Kaveri and Excavator line (i.e. covering the same segment). Is that what we should expect from AMD's new x86 uArch?

 

[Phynaz]

Who's we? I specifically said AMD needs to define how they are using the phrase.

 

[mrmt]

I think it's clear what we're talking about - replacements for the Bulldozer-based Kaveri and Excavator line (i.e. covering the same segment). Is that what we should expect from AMD's new x86 uArch?

No. They cannot afford it.

 

[NostaSeronx]

Who's we? I specifically said AMD needs to define how they are using the phrase.

AMD's definition of "High Performance" is something aimed at Supercomputing/High Performance Computing. The next CPU SoCs from AMD are specifically aimed at Exascale Supercomputing/HPC. Any dies that don't hit specific targets will be reversed binned. Which would then be given to the FX market. For you know increased profits from usage of the same chips.

 

[raghu78]

If something is too good to believe, it usually is. And with AMDs minimalistic and ever reduced R&D budget its even further away to believe.

Since you compare to Apple. Their R&D budget is 4 times greater than AMDs.

You are not getting something you didnt pay for in R&D. There isnt engineers who just magically come up on their own with completed super innovations over night for chip designs.

The ARM Cortex A15 and A57 are designed to scale up to 2.5Ghz. Jim Keller stated that K12 will be a high performance / high frequency design and will extend the performance range of ARM. Keller's expertise in designing Cyclone would be invaluable in designing K12.

AMD has beaten Intel in the past with designs like Athlon K7 and Athlon 64 K8. But AMD messed up big time with Bulldozer. Intel too has messed up in the past with Prescott (aka Presshot). But from Core 2 they have been spot on with design and execution and AMD were always behind. With Bulldozer it fell apart and AMD was no more a competition. Anyway you talk as if AMD has not designed good CPU cores at all. They have excellent engineers. The problem with Bulldozer was wrong design. That blame lies with technical leadership. These massive CPU design projects work from top - down and the key is laying down the right ideas when you come up with the high level design and there Keller will have a major impact. If you screw that phase then its game over. Keller stated that they took the best features of both their big and small cores for the new design while avoiding the weaknesses/drawbacks of each. Anyway you can continue to be skeptical about AMD so that leaves room for you to be surprised when AMD delivers with a efficient high performance core. :thumbsup:

 

[NostaSeronx]

The issue with the Dozer family was of the missed jump opportunity to G2012/C2012/FM2. Bulldozer was the right CPU design but was placed on outdated systems. There was a road to new systems but that was cancelled.

http://i.imgur.com/2yhSejN.png
http://i.imgur.com/ueWyiSu.png

 

[pTmdfx]

No. They cannot afford it.

Just the tiny truth is that even without selling many chips into the higher-margin server segment, the Bulldozer family would still likely complete its multi-year journey of 4 generations in 4-4.5 years, despite the acquisition of SeaMicro, the shrinking R&D budget and all the internal shuffles. This does not sound something really unaffordable from day one IMO.

 

[pTmdfx]

I specifically said AMD needs to define how they are using the phrase.

So far AMD uses high-performance for the Bulldozer family, high-performance, low-power for the Cat family (in some LinkedIn job postings and some employee resumes) and 64-bit ARM K12, and just low-power or ultra-low-power for the Cat family in marketing.

 

[ShintaiDK]

The ARM Cortex A15 and A57 are designed to scale up to 2.5Ghz. Jim Keller stated that K12 will be a high performance / high frequency design and will extend the performance range of ARM. Keller's expertise in designing Cyclone would be invaluable in designing K12.

AMD has beaten Intel in the past with designs like Athlon K7 and Athlon 64 K8. But AMD messed up big time with Bulldozer. Intel too has messed up in the past with Prescott (aka Presshot). But from Core 2 they have been spot on with design and execution and AMD were always behind. With Bulldozer it fell apart and AMD was no more a competition. Anyway you talk as if AMD has not designed good CPU cores at all. They have excellent engineers. The problem with Bulldozer was wrong design. That blame lies with technical leadership. These massive CPU design projects work from top - down and the key is laying down the right ideas when you come up with the high level design and there Keller will have a major impact. If you screw that phase then its game over. Keller stated that they took the best features of both their big and small cores for the new design while avoiding the weaknesses/drawbacks of each. Anyway you can continue to be skeptical about AMD so that leaves room for you to be surprised when AMD delivers with a efficient high performance core. :thumbsup:

AMD back then more or less bought entire design teams and IP for that success. Also back then AMDs R&D was much closer to Intels R&D and they had fabs and somewhat close to equal foundry abilities. And they had the pure luck that Intel was messing everything possible up in desktop and server segments. Remember, mobile segment was entirely different due to Pentium-M. AMD couldnt touch that one.

Right now it seems all the hopes for AMD is put into a single mans name. And thats not going to happen. Jim Keller wasnt the sole man behind Cyclone, also Cyclone shows less impressive results outside its cache abilities.

Unfortunately this is the same hype as we keep hearing with Phenom, Phenom 2, Bulldozer, Pilediver, Steamroller, Excavator and so on. The next one will fix everything and put AMD in the front or equal again.

AMDs last successful performance core was developed in a span of 12-17 years ago.

Again, I know this is something some keep ignoring because its a discouraging fact. But in R&D, you are not getting something you are not paying for. And AMDs R&D budget today is lower than it was 10 years ago. And its not paying for chips that will rival Qualcomm and Intel performance chips, and maybe not even nVidia GPUs.

Resources are spread so thin than you have to worry if AMD in that future will even be able to compete in a single of those segments they are now in.

 

[NostaSeronx]

So far AMD uses high-performance for the Bulldozer family, high-performance, low-power for the Cat family (in some LinkedIn job postings and some employee resumes) and 64-bit ARM K12, and just low-power or ultra-low-power for the Cat family in marketing.

High Performance;
Bulldozer
Piledriver

High Performance, Low Power;
Steamroller
Excavator
K12

Low Power;
Bobcat
Jaguar
28-nm Puma
28-nm ARMv8 Atlas(Cortex A57)

Ultra Low Power;
20-nm Puma+
20-nm ARMv8 Atlas(LP Cortex A57)
Cheetah

From what I can get from the linkedin profiles and resumes. High performance and low power being the legacy designs make use of a basic DVFS. The HPL and ULP being the novel designs make use of a complex AVFS.

AVFS is process variation aware where DVFS normally was not aware.

 

[pTmdfx]

Again, I know this is something some keep ignoring because its a discouraging fact. But in R&D, you are not getting something you are not paying for. And AMDs R&D budget today is lower than it was 10 years ago. And its not paying for chips that will rival Qualcomm and Intel performance chips, and maybe not even nVidia GPUs.

Resources are spread so thin than you have to worry if AMD in that future will even be able to compete in a single of those segments they are now in.

Then I would wonder if that included process manufacturing R&D, which should have been an order of magnitude of the chip design cost.

Today's AMD is just driving 2 in-house APUs (add one ARM CPU this year) alongside 3 GPUs to the market every year, while having the semi-custom customers to pay for their chips and perhaps also the AMD IP use license. The R&D expenses (late edit for correction) operating expense of the following quarters are not expected to shrink anymore, but in the range of $420 to $450 million. Of course one will not get more than what he is paying, but how could you be so sure if he is not paying enough, anyway? By looking at figures in the past years, which AMD was crunching out four CPU chips on a custom process, alongside canned iterations of Bulldozers and Fusion, four GPUs and also loads of research teams on Fusion architectures and CPU architectures? Or a quarter that AMD probably had all its Bulldozer MP server projects canned, or had the ARM IPs acquired? What about quarters that the actual R&D expense may be greater than the shown R&D expense, thanks to the NRE revenue from semi-custom customers?

http://www.semiaccurate.com/forums/....com/forums/showpost.php?p=194277&postcount=4
[...] So the one of the levers of the model is you seen us really take our operating expense down over the last three or four quarters as we restructure the company that restructuring is largely behind us now but what you'll see is as we accelerate revenue that the operating expense will stay constant and roughly flat and that is the leverage of the model when you model.

 

[ShintaiDK]

Then I would wonder if that included process manufacturing R&D, which should have been an order of magnitude of the chip design cost.

Today's AMD is just driving 2 in-house APUs (add one ARM CPU this year) alongside 3 GPUs to the market every year, while having the semi-custom customers to pay for their chips and perhaps additionally the architectural license cost. The R&D expenses of the following quarters are not expected to shrink anymore, but in the range of $420 to $450 million. Of course one will not get more than what he is paying, but how could you be so sure if he is not paying enough, anyway? By looking at figures in the past years, which AMD was crunching out four CPU chips on a custom process, alongside canned iterations of Bulldozers and Fusion, four GPUs and also loads of research teams on Fusion architectures and CPU architectures? Or a quarter that AMD probably had all its Bulldozer MP server projects canned, or had the ARM IPs acquired? What about quarters that the actual R&D expense may be greater than the shown R&D expense, thanks to the NRE revenue from semi-custom customers?

While AMD had a foundry business back then to do R&D for. They didnt have GPU, chipset, ARM and so on. And when you look on all competitiors, their R&D budgets have gone up 2 fold or more.

AMDs financials are pretty straight forward. Feel free to show any edvidence of any "unlisted" R&D.

NRE is not revenue, its a one time cost.

 

[pTmdfx]

While AMD had a foundry business back then to do R&D for. They didnt have GPU, chipset, ARM and so on. And when you look on all competitiors, their R&D budgets have gone up 2 fold or more.

So what? Let's say one of the main competitor that doubles the R&D expense has started a CPU project and numerous projects surrounding its SOC line by then, while AMD had reduced the numbers of chips, particularly the costly (at that time with BD) server MP projects, per year in that period. Also the cost of custom process matters.

AMDs financials are pretty straight forward. Feel free to show any edvidence of any "unlisted" R&D.

Late edited #123 for the evidence. Check the first post of that thread for the audio source if you want. Feel free to ignore the art of accounting.

NRE is not revenue, its a one time cost.

Payment for the NREE of the semi-custom chips is a revenue from AMD's standpoint, just that it is not a part of the product revenue from the accounting standpoint.

 

[ShintaiDK]

So what? Let's say one of the main competitor that doubles the R&D expense has started a CPU project and numerous projects surrounding its SOC line by then, while AMD had reduced the numbers of chips, particularly the costly (at that time with BD) server MP projects, per year in that period. Also the cost of custom process matters.

Yet you still expect AMD to deliver much more?

Late edited #123 for the evidence. Check the first post of that thread for the audio source if you want. Feel free to ignore the art of accounting.

Payment for the NREE of the semi-custom chips is a revenue from AMD's standpoint, just that it is not a part of the product revenue from the accounting standpoint.

I am not sure you even read your own link. Lisa Su says the exact same as me.

NRE is the cost of a product with no further development. And NRE will be under R&D. Revenue from the NRE will be under revenue for the company.

You can read more about NRE here if you are still uncertain of what it is:
http://www.shefer.net/Articles/Non_Recurring_Engineering.pdf

 

[krumme]

No. They cannot afford it.

Not by a long stretch. But even if they could, they would never use the money on something like that.
Who wants to invest their pension savings on a new huge x86 core design? lol

The entry cost to highend server goes far beyond a high perf ipc core design needed to keep software licensing low, and at the same time getting compettitive perf/watt performance. Threatening Intel here, is also going to war to Intels marginal cost on its gigantic process and fab investments. Add brand value, compilers, and a firm grib on OEM and long term sales connections, and you must bring a bigger wallet than anyone have ever remotely invested in this industry before.

For a potential benefit that will potentially fade to nothing in 10-15 years. No way.

.....

(Perhaps if Dirk Meyers had the money to try...🙂)

 

[frozentundra123456]

Funny how this thread morphed from a statement by an AMD executive that they were basically not going to compete against in the high end into another "Keller is magic" and is going to beat Intel projection. We will see, it is not impossible, but seems highly unlikely.

And 2016, assuming (big assumption) that there are no delays, is two years away. AMD currently has no ARM processor and trails intel in absolute performance and performance per watt, especially in the big core line. Intel and the the ARM competitors are not going to stand still for the next 2 years either. So even if AMD comes out with a chip that can match what Intel or ARM has now, they will still trail in 2016 or even later when the chip actually comes out.

 

[pTmdfx]

Yet you still expect AMD to deliver much more?



I am not sure you even read your own link. Lisa Su says the exact same as me.

NRE is the cost of a product with no further development. And NRE will be under R&D. Revenue from the NRE will be under revenue for the company.

You can read more about NRE here if you are still uncertain of what it is:
http://www.shefer.net/Articles/Non_Recurring_Engineering.pdf

Now what I am saying is basically that the customer will pay the quarterly NREE before the product launches, and this will not be reflected in the financial statement explicitly, nor a part of the "net revenue" of the final products, but "hidden" behind or, more precisely, combined into the aggregate R&D expense. This was what she meant. God knows who didn't read carefully.

 

[NTMBK]

Funny how this thread morphed from a statement by an AMD executive that they were basically not going to compete against in the high end into another "Keller is magic" and is going to beat Intel projection. We will see, it is not impossible, but seems highly unlikely.

This thread was started by a poster misunderstanding that Anandtech were displaying a slide from over two years ago, not a new "statement by an AMD executive".

 

[pTmdfx]

Yet you still expect AMD to deliver much more?

Did I? It is "much more" in your view but not mine. It has already been developing two microarchitectures in parallel for years, while there shall be much more commonalities/potential in sharing budgets between the two projects as claimed.

By the way, just in case someone gets short circuited, I expect neither an x86 SOC at the scale of those upcoming EP/EX chips from Intel, nor an x86 SOC clocked like 125W Bulldozer, Devil Canyon, or Richland in the past. Though FinFET may help the frequency scaling a bit. Anyway, god knows why people like to equalize the "high performance big core" tag with just these super high end battlefields.