[ASML] Intel to introduce EUV in 2016

[witeken]

1: Your date is wrong. 2 years instead of months.

2: He didn't say 10 wouldn't be ready.

3: That negatively impacts the credibility of your argument.

 

[dahorns]

2: Two months ago, Mark Bohr said EUV was not going to be ready for 10nm. I don't believe this changed within two months.

This is incorrect. He said he couldn't count on EUV being ready for 10nm. This fits perfectly with the concept that they'll have 10nm ready to go without EUV, but will move over to EUV mid node if it becomes available.

As far as I know, Intel is the only one really targeting a 10nm release that would fit in the 2016 time frame.

 

[Khato]

I'd also lean towards the statement being in reference to TSMC.

The argument that it has to be in reference to Intel because of the date depends upon the interpretation of the statement. Specifically, does the "expected in late 2016" refer to when the "mid-node insertion of EUV at the 10nm logic node" will occur or does it only refer to "the 10nm logic node"? I'd expect that it's meant to be interpreted as 'mid-node insertion of EUV' at 'the 10nm logic node expected in late 2016' which matches with TSMC's optimistic roadmap for starting their '10nm' risk production.

 

[witeken]

Does Idontcare know the definition of mid-node? Is it correct that mid-node actually means pre-node in the semiconductor industry?

Oh, wait. He already replied to this thread.

Mid-node insertion means the node will already be in production and this would qualify as a post-production requal.

Nope, it seems like semiconductor people do know the difference between middle and something that is not in the middle.

 

[AtenRa]

1: Your date is wrong. 2 years instead of months.

2: He didn't say 10 wouldn't be ready.

3: That negatively impacts the credibility of your argument.

yea sorry wrong link,

Correct link was fixed in my post, see correct link also bellow

http://www.eetimes.com/document.asp?doc_id=1323865

 

[AtenRa]

I'd also lean towards the statement being in reference to TSMC.

The argument that it has to be in reference to Intel because of the date depends upon the interpretation of the statement. Specifically, does the "expected in late 2016" refer to when the "mid-node insertion of EUV at the 10nm logic node" will occur or does it only refer to "the 10nm logic node"? I'd expect that it's meant to be interpreted as 'mid-node insertion of EUV' at 'the 10nm logic node expected in late 2016' which matches with TSMC's optimistic roadmap for starting their '10nm' risk production.

Yes one interpretation could be this one. Of course we also have Samsung that could also be the second player here. But clearly, the topic tittle is wrong and mrmt should fix it.

 

[Idontcare]

Doesn't really matter which company, what matters is the timing.

If timing is late 2016 then that is 2 years away still, a lot can go wrong (or simply not go at all) in 2 years.

 

[AtenRa]

Doesn't really matter which company, what matters is the timing.

If timing is late 2016 then that is 2 years away still, a lot can go wrong (or simply not go at all) in 2 years.

Agreed, we haven't even seen any 20nm/16nm or even 14nm products in retail yet.

 

[Ajay]

Doesn't really matter which company, what matters is the timing.

If timing is late 2016 then that is 2 years away still, a lot can go wrong (or simply not go at all) in 2 years.

If EUV development finally has traction, then there are also things that can go right - though at a 44W terminal output, EUV is still along way from the sought after 100W goal.

I think Bohr has really written off EUV for 10nm. If 10nm is progressing well with some quad patterning - and provides Intel with financially acceptable cost/wafer - I don't see why they would change their 10nm production model. It seems like such an introduction would break Intel's 'copy exact' development to manufacturing model. I'm inclined to think that Intel will want to start a new process with EUV from the start - please feel free to correct me if I'm wrong.

Given Bohr's apparent risk adverse approach, a successful 24 hr stress test is just one data point. I would think ASML will need to prove, at least in a prototype manufacturing module for a given node, that EUV delivers long term reliability with acceptable down time for maintenance. The news is just a baby step - and likely reason that EUV won't meet Intel's goals by the time 10nm goes into production. I think you have said it takes around four years to move from R&D to HVM for a given node - so the next logical target would be 7nm - and even then the timing is tight.

Thanks for your continued good humor WRT amateur analyses like mine

 

[AtenRa]

This is a nice link

http://semimd.com/blog/tag/10nm/

The conference opened Tuesday, Sept. 16, with the keynote presentation by Martin van den Brink, the president and chief technology officer of ASML Holding. His talk, titled “Many Ways to Shrink: The Right Moves to 10 Nanometer and Beyond,” was clearly meant to provide some reassurance to the attendees that progress is being made with EUV.

He reported his company’s “30 percent improvement in overlay and focus” with its EUV systems in development. ASML has shipped six EUV systems to companies participating in the technology’s development (presumably including Intel, Samsung Electronics, and Taiwan Semiconductor Manufacturing, which have made equity investments in ASML), and it has five more being integrated at present, van den Brink said.

The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.

The ASML executive predicted that chips with 10nm features would mostly be fabricated with immersion lithography systems, with EUV handling the most critical layers. For 7nm chips, immersion lithography systems will need 34 steps to complete the patterning of the chip design, van den Brink said. At that process node, EUV will need only nine lithography steps to get the job done, he added.

lots of info here

 

[witeken]

Doesn't really matter which company, what matters is the timing.

But I'd like to know, that's what this discussion is about, right.

If timing is late 2016 then that is 2 years away still, a lot can go wrong (or simply not go at all) in 2 years.

ASML seems to be ahead of its schedule. I haven't read any bad news about EUV so far in 2014.

I think Bohr has really written off EUV for 10nm.

Why would he? If EUV delivers on its promises then it would be welcomed by everyone.

If 10nm is progressing well with some quad patterning - and provides Intel with financially acceptable cost/wafer - I don't see why they would change their 10nm production model. It seems like such an introduction would break Intel's 'copy exact' development to manufacturing model. I'm inclined to think that Intel will want to start a new process with EUV from the start - please feel free to correct me if I'm wrong.

Because quad patterning has a massive cost, including the cost of yields.

You have a point, though. If Intel's 10nm is already in production, that probably means they don't have yield issues anymore and development costs are done, so maybe the ROI of changing mid-node simply isn't there, but according to this article, apparently it is.

Given Bohr's apparent risk adverse approach, a successful 24 hr stress test is just one data point. I would think ASML will need to prove, at least in a prototype manufacturing module for a given node, that EUV delivers long term reliability with acceptable down time for maintenance. The news is just a baby step - and likely reason that EUV won't meet Intel's goals by the time 10nm goes into production. I think you have said it takes around four years to move from R&D to HVM for a given node - so the next logical target would be 7nm - and even then the timing is tight.

I see it much differently. This seems quite a major milestone in the development of EUV, it confirms EUV's good health. This news conflicts with your assumptions that it won't meet Intel's goals, 7nm will be tight, etc.

BTW, the post above from AtenRa makes a good point: Intel didn't invest in ASML for nothing. http://newsroom.intel.com/community...tion-semiconductor-manufacturing-technologies

The objective is to shorten the schedule for deploying the lithography equipment supporting these technologies by as much as two years, resulting in significant cost savings and other productivity improvements for semiconductor manufacturers.

 

[witeken]

This is a nice link

http://semimd.com/blog/tag/10nm/



lots of info here

Interesting. Now, do we need any further confirmation that it's indeed Intel?

 

[NTMBK]

Exciting news! There's been too many delays in EUV, it'll be good to see it finally arrive. I assume it's Intel, because who else will have 10nm at "mid-node" in 2016?

 

[krumme]

This is extremely good news for everyone.

 

[krumme]

Ah, I misread it as the 10nm logic node was to be released in late 2016.

Dont be sorry. We get the names of the companies mixed sometimes also.

 

[Idontcare]

But I'd like to know, that's what this discussion is about, right.

My point was just that arguing over the specific company to whom the ASML rep was referring is likely to be a fruitless speculative endeavor compared to the more intriguing discussion to be had regarding the 10nm HVM timeline and the risk/reward intricacies that are to be comprehended in the project management side of performing a mid-node insertion effort.

Of course everyone would like to know which company the ASML rep was referring to, and we can certainly flesh out the spectrum of contenders and assign a weighted probability matrix to the topic.

My money would be on this being Intel, with TSMC being a distant second-choice.

But for some reason though this type of "gentlemen's speculation" becomes too rancorous around here for my blood, so my natural inclination is steer towards discussion material that is less speculative and more cogent.

FWIW, be prepared for a veritable onslaught of EUV "news" here over the next 2 weeks, the 2014 International Symposium on Extreme Ultraviolet Lithography is hosted next week (Oct 27-29) and that means a lot of "good" news has been bottled up for presentations, the kind of news that marketing teams are frothing at the mouth to be allowed to go public with so they can do what they are paid to do. (case in point, the ASML rep's motivation for dropping the news about 10nm mid-node insertion)

 

[III-V]

Doesn't really matter which company, what matters is the timing.

If timing is late 2016 then that is 2 years away still, a lot can go wrong (or simply not go at all) in 2 years.

Certainly that is true, but for once, the news I've seen about EUV has been consistently good over the past year, sans TSMC's little kablooey in Q1

ASML's actually ahead of their goal of 500 wph for the year, and hopefully things continue to go well over the next year and a half.

 

[NostaSeronx]

http://electroiq.com/euvl-focus/2014/03/04/state-of-euvl-challenges-of-hvm-introduction/

In their paper, GLOBALFOUNDRIES compared EUVL and ArF immersion scanners for 20/14 nm metal lines and found equal yields for both lithography techniques. They did note an additional issue of EUV mask backside contamination, which I believe can be addressed. For 10/7 nm metal lines, they believe they need to address issues of overlay, mask defects, integration and line width roughness (LWR) through focus, in order to bring EUVL into production.

It was evident from the talk by TSMC, which reported ~10 W of power instead of the expected 30 W for their planned insertion of EUVL into the 10 nm node. A laser misalignment caused a source breakdown and a two-week unexpected downtime for the tool. This did not make TSMC happy, but did cause some trade journalists not known for their support of EUVL to announce that “EUVL suffers new setback” when it clearly had not. A brand new tool’s first installation in the field can be expected to have glitches and downtime; expecting anything else is not realistic. (More comments on source are given below.) TSMC also reconfirmed their commitment to bring EUVL into HVM at the 10 nm node.

Mark Philips of Intel, in his talk, outlined the 1-D grating and cuts approach of Yan Borodovsky. EUVL is the preferred choice for cuts as EUVL offers advantages in terms of number of masks and edge placement error (EPE). Intel still plans to insert EUVL at the 7 nm node in 2017, but needs a mature COO for EUVL.

The only two going for EUV at 10-nm are TSMC and Samsung/GlobalFoundries.

Samsung/GlobalFoundries are the only one to get 10-nm FinFETs in 2016. Thus, indicating that TSMC is waiting for EUV for 10-nm. While, Samsung/GlobalFoundries will be doing ArF and EUV versions of 10-nm.

10-nm LPe(Low Power Early) = ArF
10-nm LPP(Low Power Plus) = EUV
etc.

Samsung is 1st, then GlobalFoundries is 2nd. TSMC is then 3rd, and Intel is 4th. Intel doesn't matter as quad-patterning will give them the technical feat award.

 

[witeken]

compared to the more intriguing discussion to be had regarding the 10nm HVM timeline and the risk/reward intricacies that are to be comprehended in the project management side of performing a mid-node insertion effort.

Those are of course also interesting things to know if someone has any knowledge about that he can share.

 

[jdubs03]

http://electroiq.com/euvl-focus/2014/03/04/state-of-euvl-challenges-of-hvm-introduction/The only two going for EUV at 10-nm are TSMC and Samsung/GlobalFoundries.

Samsung/GlobalFoundries are the only one to get 10-nm FinFETs in 2016. Thus, indicating that TSMC is waiting for EUV for 10-nm. While, Samsung/GlobalFoundries will be doing ArF and EUV versions of 10-nm.

10-nm LPe(Low Power Early) = ArF
10-nm LPP(Low Power Plus) = EUV
etc.

Samsung is 1st, then GlobalFoundries is 2nd. TSMC is then 3rd, and Intel is 4th. Intel doesn't matter as quad-patterning will give them the technical feat award.

Interesting, so somehow all of those companies just blast past Intel in releasing 10nm? Something sounds wrong about that, considering Intel has been working on 10nm before anyone else.

This stuff is all conjecture, there is no point going on and on about something that could easily change in the future.

 

[NostaSeronx]

Interesting, so somehow all of those companies just blast past Intel in releasing 10nm?

1st/2nd Samsung/GlobalFoundries -> 10-nm EUV (LPe, 10-nm first SKU will be ArF/10-nm LPP, EUV)
TSMC -> 10-nm EUV (FF, 10-nm first SKU will be EUV)
Intel -> 7-nm is planned to be EUV, but they can always use Octo-patterning for 7-nm. If O-P is used Intel is more likely to skip to Directed Self Assembly lithography for 5-nm.

Intel is part of the DSA Lithography Consortium, so it makes sense to skip EUVL and EBL.

Something sounds wrong about that, considering Intel has been working on 10nm before anyone else.

I'm talking in regards to EUV. In which, Samsung/GlobalFoundries will be first.

 

[Ajay]

This is a nice link

http://semimd.com/blog/tag/10nm/

The light source being developed by ASML’s Cymer subsidiary has achieved an output of 77 watts, he said, and the company expects to raise that to 81 watts by the end of 2014. The key figure, however, remains 100 watts, which would enable the volume production of 1,000 wafers per day. No timeline on that goal was offered.

lots of info here

Yes, but I bolded a key line in that statement. So Cymer already has a an EUV light source with a terminal output of 77 watts and ASML expects to have a system operating at 81W by years end (not very far away). This strikes me as overly indulgent and highlights why a timeline for the 100W goal is indeterminate and brings into question the viability of the HVM availability in 2016. ASML is not on a standard engineering pathway for it's EUV systems yet. In other words, they don't have a simple roadmap of well identified milestones. I would speculate, that there are numerous parametric issues (where a change in one sub-system creates the need to change many more) which will require complex and, as of yet, unknown solutions at each iteration which still may require additional R&D. These issues are not likely to be strictly limited to the laser system, but also the integration into fab module (variation in dimension, geometry, mass, etc.). This all needs to be done with an incredible level of precision and accuracy to meet sub 14 nm semicon manufacturing needs. The 2016 date is an estimated target date only; based on the expectation of a relatively uninterrupted development and qualification progression.

Please understand that I'll be happy when EUV meets semicon manufacturers financial goals for entry into mass production. It just seems to me that the press generated by ASML is too dominated by standard marketing hype (as expected) and I'm not ready to throw a party, yet, for a technology that has had such a long and troubled development path.

 

[witeken]

1st/2nd Samsung/GlobalFoundries -> 10-nm EUV (LPe, 10-nm first SKU will be ArF/10-nm LPP, EUV)
TSMC -> 10-nm EUV (FF, 10-nm first SKU will be EUV)
Intel -> 7-nm is planned to be EUV, but they can always use Octo-patterning for 7-nm. If O-P is used Intel is more likely to skip to Directed Self Assembly lithography for 5-nm.

Intel is part of the DSA Lithography Consortium, so it makes sense to skip EUVL and EBL.I'm talking in regards to EUV. In which, Samsung/GlobalFoundries will be first.

So Intel invested a few billions USDs in ASML to accelerate EUV by 2 years only to see that 3 other companies will use the technology, (partially) generated by its money, before they'll use it? That's harsh.

 

[NostaSeronx]

So Intel invested a few billions USDs in ASML to accelerate EUV by 2 years only to see that 3 other companies will use the technology, (partially) generated by its money, before they'll use it? That's harsh.

"Accelerating EUV technology development to enable its successful implementation in high volume manufacturing for the 32nm node in 2009 is a critical mission at Intel," said Intel Fellow Peter Silverman of that investment.

http://www.theregister.co.uk/2004/01/27/intel_pumps_20m_into_euv/

It hasn't worked before, and it won't work now.

“DSA is making remarkable progress and is gaining momentum in the market. At SPIE, for example, Intel and others formed a new DSA consortium. In addition, GLOBALFOUNDRIES, IBM, Samsung and TSMC are still working on DSA in R&D, but vendors are keeping their cards close to the vest. Still, the consensus among chipmakers is that DSA could be ready for high-volume manufacturing at 7nm or 5nm. ’Intel is talking about an introduction at the 5nm node. I have the feeling that the memory people could introduce it sooner, maybe in 2015 to 2016,' said Serge Tedesco, lithography program manager at CEA-Leti, which is also part of the new DSA consortium with Intel.” In addition, LaPedus highlighted that “DSA is also disruptive and threatens the status quo, because the process isn’t dependent on costly lithography. In fact, DSA makes use of existing lithography tools. All the key processing steps are conducted in a wafer track system. Using 193nm immersion lithography, DSA has demonstrated the ability to pattern structures down to 12.5nm. The industry also is working on next-generation, high chi materials, which could extend the technology beyond 12.5nm, thereby pushing out the need for extreme ultraviolet (EUV) lithography. By most accounts, though, DSA will not appear until 7nm.”

SPIE Spring 2014

ASML is also in the DSAL Consortium, so $1 billion for EUV and 450mm and $3 billion for DSA.

 

[witeken]

ASML wants to double revenue by 2020 to $10B, sold first EUV machine for commercial use to TSMC.

LONDON, 24 November 2014 - At its Investor Day, ASML Holding N.V. (ASML) will today outline its expected opportunity to grow net sales to about EUR 10 billion and to triple earnings per share by 2020.

ASML also announces that Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) has ordered two NXE:3350B EUV systems for delivery in 2015 with the intention to use those systems in production. In addition, two NXE:3300B systems already delivered to TSMC will be upgraded to NXE:3350B performance.

Regarding our main technologies, we expect

* Deep-UV immersion systems to be used for patterning of multiple layers in all advanced processes for the forseeable future;
* EUV to enable cost effective manufacturing of logic, DRAM and NAND chips from 2016/2017 allowing feature size shrink and simplification of manufacturing processes;
* Holistic Lithography products to deliver advanced correction capability supporting the tightening of litho related manufacturing tolerances, resulting in lower rework and higher yields.