ASML buys Cymer (EUV tech stuff)

[Lonyo]

http://www.eetimes.com/electronics-...4398841/ASML-doubles-down-on-EUV?pageNumber=0

ASML is the company which asked Intel, Samsung and TSMC to invest in it for 450mm wafers.
Now they have bought a light source company in order to aid them with their development of EUV, which is useful for continued scaling down.

Seems like there could be some roadblocks ahead with EUV if they can't make it work, especially when it seems like they need to increase the speed of the process 10x for it to be reasonably usable.

 

[Ajay]

Wow, and ASML has been working on EUV since 1997. AFAIK, Intel can't get to 10nm without EUV - and they wanted to use it their 2014 14nm tick.

 

[MisterMac]

Well now we know why intel splashed the cash as fast as possible.


Clearly EUV is falling behind on the tick tock schedule - and intel waits for no one.

 

[soccerballtux]

Wow, and ASML has been working on EUV since 1997. AFAIK, Intel can't get to 10nm without EUV - and they wanted to use it their 2014 14nm tick.

they can just takes like quad patterning and other silly things.

 

[Idontcare]

Wow, and ASML has been working on EUV since 1997. AFAIK, Intel can't get to 10nm without EUV - and they wanted to use it their 2014 14nm tick.

The original EUV charter called for EUV for 65nm.

The only reason we managed to live without EUV until now is because TSMC stood up and pushed hard for immersion-litho to become a reality. That made 193nm-immersion credible, versus merely being an academic curiosity, and it was immersion litho that made 45nm and 32nm possible.

Even then we had to go to double-patterning with the immersion litho.

The crazy part about EUV is that it is so delayed, so ridiculously delayed, that even when it finally comes out in production it will be pushed to its own intrinsic limits nearly immediately. EUV won't have but one or two nodes before Intel will have no choice but to resort to the same double-patterning shenanigans again with EUV.

Scaling is slamming hard up against a wall in the coming decade. With or without EUV.

 

[MisterMac]

The original EUV charter called for EUV for 65nm.

The only reason we managed to live without EUV until now is because TSMC stood up and pushed hard for immersion-litho to become a reality. That made 193nm-immersion credible, versus merely being an academic curiosity, and it was immersion litho that made 45nm and 32nm possible.

Even then we had to go to double-patterning with the immersion litho.

The crazy part about EUV is that it is so delayed, so ridiculously delayed, that even when it finally comes out in production it will be pushed to its own intrinsic limits nearly immediately. EUV won't have but one or two nodes before Intel will have no choice but to resort to the same double-patterning shenanigans again with EUV.

Scaling is slamming hard up against a wall in the coming decade. With or without EUV.

Very interesting.

So your take on the whole thing is - cause of the massive delays and negligence if you will - from the players to push EUV will cause EUV to be useless stepping stop.

Due to the fact that EUV by the time it's used will be stretched thin of it's physical\theoretical limits?


What's Intels endgame plan here? - they need to show everyone else how to manufacture or they loose a LARGE part of their machinery to compete.

Will they have graphene incheck by then?

 

[Idontcare]

EUV won't be useless, it will be intersecting its own "value-add" position much later in its total lifetime cycle is all.

All the stuff that EUV was going to make become easy for the process guys has already been dealt with by making the immersion-litho work and by making double-patterning commercially viable.

14nm is expected to have at least quadruple patterning step in it.

Putting all these backup plans into action raises the cost of node development as well as the cost per wafer once the node is in production. EUV will help whenever it finally gets into production but the value-add of EUV as a technology continues to slip away.

But yes, the bottom line is that regardless what manner of lithography employed the litho itself does not change the fact that we are down to 14nm without it and ~5nm is the end-game for physical scaling.

After 5nm we will see process nodes transition into what is essentially a performance-rating or "PR" numbering scheme (we may already be seeing that at GloFo with their so-called 14XM node) in which computing density will still increase and electrical performance will still improve (lower leakages, higher drive currents, etc) but it won't be coming from shrinking of the components because shrinking itself will be physically impossible at that point.

And it is at that point, which is not in the too distant future, in which litho stops being a technology enabler and instead becomes purely a cost-reduction tool. So EUV has a rather narrow time-window for the industry as a technology enabler, but it is a healthy decade which is more than enough time for people to make tons of money as businesses and as individuals.

 

[cbn]

After 5nm we will see process nodes transition into what is essentially a performance-rating or "PR" numbering scheme (we may already be seeing that at GloFo with their so-called 14XM node) in which computing density will still increase and electrical performance will still improve (lower leakages, higher drive currents, etc) but it won't be coming from shrinking of the components because shrinking itself will be physically impossible at that point.

IDC, Thanks for the info. What you are mentioning sounds like it will be a very interesting topic for the future.

P.S. I found the following information on the relationship of drive current to other factors (including the leakage you mentioned) http://en.wikipedia.org/wiki/High-k_dielectric#Gate_capacitance_impact_on_drive_current

(Based on my understanding) As VDD (Supply voltage) decreases, threshold voltage must also decrease in order to maintain drive current. The trade-off is that as threshold voltage decreases....leakage increases....resulting in higher standby power consumption.

Other factors, including channel length and gate dielectric are mentioned as well.

Another article ---> http://ambienthardware.com/courses/tfe01/pdfs/Roy1.pdf

I. INTRODUCTION
To achieve higher density and performance and lower
power consumption, CMOS devices have been scaled for
more than 30 years. Transistor delay times decrease by more
than 30% per technology generation, resulting in doubling
of microprocessor performance every two years. Supply
voltage (VDD) has been scaled down in order to keep the
power consumption under control. Hence, the transistor
threshold voltage (VTH) has to be commensurately scaled
to maintain a high drive current and achieve performance
improvement. However, the threshold voltage scaling results
in the substantial increase of the subthreshold leakage
current [1].

If anyone has better articles applicable to "CPU" (particularly those aimed at lay people) please post away. I realize I don't have the best understanding when it comes to xtors

 

[cbn]

Great Article from Anand in 2007! (With discussion of drive current vs. leakage)

http://www.anandtech.com/show/2161/2

When the transistor is on, current is allowed to flow from one terminal to the other (source to drain), and when it is off current shouldn't flow. Making enough current flow when it should and minimizing the amount that flows when it shouldn't is one of the major hurdles to making smaller transistors that run cooler/faster.

The voltage present at the Gate and the Source will determine whether or not current will flow in the transistor. Intel's 45nm process makes significant changes to two of the components in this transistor diagram: the gate electrode and the gate dielectric.

You can probably guess that as transistors get smaller, all of the parts of the transistor get smaller as well. The problem is that when some of these features get too small, they start behaving inappropriately. Case in point is the gate dielectric; with Intel's 90nm and 65nm processes, the gate dielectric was shrunk to a thickness of 1.2nm - the equivalent of about 5 atoms. The benefit of a very thin gate dielectric is that it increases the gate field effect, which increases drive current and reduces Source-drain leakage current. However, with such a thin gate dielectric electrons can tunnel directly through the layer and show up as leakage current - in other words, current would flow when it was not supposed to, translating into power wasted. On an individual transistor scale it's not such a big deal, but when you keep in mind that Penryn will have around 410 million of these transistors (820 million for quad-core) the leakage current/power draw does add up.

At 1.2nm, the gate oxide/gate dielectric in Intel's 90nm and 65nm transistors was as thin as Intel could make it without losing a great deal of power due to gate oxide leakage current. In order to make the move to 45nm Intel had to do something to thin the gate oxide without drastically increasing gate oxide leakage current.

Intel solved the gate oxide leakage problem by replacing the SiO2 gate dielectric with a material that has a higher k-value, in this case a Hafnium based material. A high-k dielectric here actually increases drive current at the same thickness as the previous SiO2 dielectric, while reducing gate leakage as well. Intel isn't disclosing how thick the Hafnium gate dielectric layer is in its 45nm transistors, but we do know that it is thicker than the 1.2nm SiO2 gate dielectric used in previous 90nm and 65nm transistors.

The second problem Intel is addressing with its 45nm transistors is a fundamental issue with the polysilicon gate electrode. The role of the gate electrode is important as it is what enables current to be driven through the transistor and as such it plays a role in how much current can be delivered. The polysilicon material that the gate electrode is made of has a tendency to form a region of depleted conducting carriers at the bottom of the gate, which reduces the drive strength of the transistor (less current flows when it needs to).

Intel's new 45nm transistors solve this problem by replacing the polysilicon gate electrode with a metal gate electrode, which completely eliminates the depleted region thus increasing the drive current.

Intel has been researching this High-k + Metal Gate (HK+MG) combination in transistors for a handful of years now, with hundreds of material options for metal gate electrodes and high-k dielectrics. The actual combination of high-k and metal gate material isn't being disclosed at this time, most likely to protect Intel's research and maintain the manufacturing advantage as long as possible. Intel expects that no other company will have HK+MG transistors until they reach 32nm or later.

The tangible advantages of these changes in materials in combination with the smaller 45nm process are quite large. According to Intel, the move from 65nm to 45nm yields a 30% reduction in transistor switching power because of the simple fact that smaller transistors have less parasitic capacitance and require less power to switch on and off.

Because of the combination of a high-k dielectric and the metal gate electrode, Intel is quoting a greater than 20% improvement in switching speed compared to its 65nm transistors. At the same speed as its 65nm transistors, there's a greater than 5x reduction in source-drain leakage power and a greater than 10x reduction in gate oxide leakage power; the latter is due entirely to the use of a high-k dielectric in the transistor. The end results of all of this are more power efficient processors, the first of which we should see by the end of this year.

P.S. IDC, I don't mean to take this EUV thread on a tangent......but your comments about 5nm (and the end of the node shrinks) really got me wondering about how performance will be scaled in the future.

 

[cbn]

they can just takes like quad patterning and other silly things.

Yes, according to the information in this EE Times article Intel will be able to do 10nm with 193nm immersion and quadruple patterning.

 

[Ajay]

Yes, according to the information in this EE Times article Intel will be able to do 10nm with 193nm immersion and quadruple patterning.

Thanks for the link. I wonder what this is going to do to wafer transit times @ 10nm?!

 

[Ajay]

And it is at that point, which is not in the too distant future, in which litho stops being a technology enabler and instead becomes purely a cost-reduction tool. So EUV has a rather narrow time-window for the industry as a technology enabler, but it is a healthy decade which is more than enough time for people to make tons of money as businesses and as individuals.

So, same as 450mm wafers, just a cost reducer. Lots of interesting stuff - I'd like to look into it more, but I've got to do some research so I can pick a topic for an advanced networking paper

 

[Idontcare]

Thanks for the link. I wonder what this is going to do to wafer transit times @ 10nm?!

I was surprised to read the following in that link:

EUV is later than I would like, and I can’t count on it for sure,

Can't count on it for sure? Damn, that is the exact opposite of a ringing endorsement.

You expect ASML to sing sweet praises for EUV, they have a natural conflict of interest there.

But to hear Intel's director of Technology speak of it in the 11th hour as still not being a sure thing - at any point down the road - really speaks volumes.

 

[Ajay]

I was surprised to read the following in that link:



Can't count on it for sure? Damn, that is the exact opposite of a ringing endorsement.

You expect ASML to sing sweet praises for EUV, they have a natural conflict of interest there.

But to hear Intel's director of Technology speak of it in the 11th hour as still not being a sure thing - at any point down the road - really speaks volumes.

Yep, that caught my eye too! TSMC my be in a tougher bind visa vi EUV when it comes to adding value as a stand-alone fab: TSMC_450mm_Fabs_and_EUV_Lithography_Critically_Important_for_10nm_7nm_Nodes

 

[cbn]

The crazy part about EUV is that it is so delayed, so ridiculously delayed, that even when it finally comes out in production it will be pushed to its own intrinsic limits nearly immediately. EUV won't have but one or two nodes before Intel will have no choice but to resort to the same double-patterning shenanigans again with EUV.

Eventually I would imagine foundries will want tools to allow single patterning on 7nm and 5nm then.

Maybe 6.7nm EUV will be able to do this....with less computational lithography needed for support?

 

[cbn]

Thanks for the link. I wonder what this is going to do to wafer transit times @ 10nm?!

That is a good question.

Does anyone know if 193nm immersion exposure time is the same for each pass needed? (ie, Will the exposure time of Quadruple patterning in 2016 for Intel take twice as long as the exposure time for double patterning in 2014 etc.)

P.S. For anyone wanting to know more about how exposure works in the process of making chips here is a post with some information : http://forums.anandtech.com/showpost.php?p=33867142&postcount=2

 

[cbn]

More (very complicated, but detailed) info here on multi-patterning I found here.....not sure what to make of it yet, but from what I see it looks like even 2.5nm is possible----> http://en.wikipedia.org/wiki/Multiple_patterning

The extrapolation of double patterning to multiple patterning has been contemplated, but the issue of cost control is still on the minds of many. While the benefits of multiple patterning in terms of resolution, depth of focus and lithographic defect sensitivity are understood, there is added burden to control the process budget increase and maintain good yield.

Beyond double (2X) patterning, the most frequently published multiple patterning methodology is the repeated spacer approach, which can be practiced in many forms.[16][17][18][19][20] A multilayer-on-topography spacer-type approach also offers some flexibility.[21] It is also possible to additively combine two or more of the above approaches. For example, a dual-tone photoresist with pitch-halved acid profile, plus dual-tone development that dissolves the highest and lowest acid concentrations, combined with a spacer process, would result in 8x pitch resolution enhancement,e.g., 40 nm half-pitch reduced to 5 nm half-pitch. Subsequently repeating the spacer process would give 16 x pitch resolution improvement, e.g., 40 nm half-pitch reduced to 2.5 nm half-pitch. The European LENS (Lithography Enhancement Towards Nano Scale) project[22] is targeted toward implementation of both double exposure (resist freezing) and spacer-based process, in principle enabling two ways of patterning for ~20 nm design rules with current lithography tools, already tailored for double patterning[23] or ~10 nm design rules in combination.[24] With successful dual-tone development of a dual-tone photoresist, 2.5 nm design rules can be imagined.

Intel used several spacer deposition/etch/clean steps to demonstrate spacers spaced apart by ~26 nm.[25] It represents a reduction of the original patterned pitch by a factor of ~1/4 and indicates that wavelength and optics no longer purely determine the lithographic resolution.

IMEC has indicated that in the event that EUV lithography is not ready, quadruple patterning (with tighter overlay specifications) would be used.[26]

At the 2010 Flash Memory Summit, it was projected that immersion lithography with multiple patterning would be used to scale NAND Flash to below 20 nm within a few years.[27]

 

[cbn]

Regarding the possibility of 2.5nm lithography mentioned above in post #17, I found this paper mentioning the difficulties of physically implementing 5nm (which is approximately 4x less dense than 2.5nm!!!) ---> http://rsfq1.physics.sunysb.edu/~likharev/personal/NanoGiga.pdf

Further scaling, all way down to » 5-nm-long channels, is also
physically possible, but leads to an extremely high
sensitivity of transistor characteristics (in particu-
lar its gate threshold voltage Vt) to minute varia-
tions of geometric dimensions. This sensitivity will
probably lead to unacceptable cost of fabrication
facilities and, as a result, to the necessity of trans-
fer to alternative electron devices in order to con-
tinue the Moore-Law-type exponential progress.

 

[Idontcare]

Yep, that caught my eye too! TSMC my be in a tougher bind visa vi EUV when it comes to adding value as a stand-alone fab: TSMC_450mm_Fabs_and_EUV_Lithography_Critically_Important_for_10nm_7nm_Nodes

Morris Chang is to TSMC as Steve Jobs was to Apple.

If that guy dies it will be the end of TSMC. Nearly was when he tried to step down the last time around (resulting in the 40nm catastrophe).

He ran TI's fabs through the 70's. Then in the late 70's he tried to convince management to go into the foundry business. They didn't like the idea, so he left and shortly thereafter founded TSMC with the backing of the Taiwanese government.

The man is a true business genius. As is Dr. Shang-Yi Chiang (Sr. VP of R&D) who also stepped out of TSMC in 2006, who's absence in-part precipitated in the 40nm debacle.

 

[Idontcare]

Regarding the possibility of 2.5nm lithography mentioned above in post #17, I found this paper mentioning the difficulties of physically implementing 5nm (which is approximately 4x less dense than 2.5nm!!!) ---> http://rsfq1.physics.sunysb.edu/~likharev/personal/NanoGiga.pdf

That sounds about right. Historically (going back for 30 yrs) the absolute leading edge of prototype feasibility exploration in the pure research space has generally probed the frontier that was 1/10 the leading edge of whatever was in production.

Leading edge in production now is Intel's 22nm, so it meets expectation that absolute leading edge R&D at the academic level is finding pathways that suggest 1/10 of 22nm (~2.5nm) is at least technically feasible from the standpoint of applied physics.

R&D in the semiconductor industry is usually not about finding and determining the leading edge of technical capability in terms of physics, the universities do that part.

Rather, R&D in the semiconductor industry is about making the technically feasible become the economically viable.

The time it takes to make that happen is generally 10yrs, give or take.

 

[cbn]

Deleted.

 

[cbn]

This article was originally posted Feb 3rd, 2012, but I am including because it specifically mentions the improvements being made to 193nm immersion scanners....in order to increase throughput and reduce the impact on transit times of having to do multiple exposures.

http://semimd.com/blog/2012/02/03/cymer’s-euv-power-source-roadmap-slips/

Cymer’s EUV Power Source Roadmap Slips

By Mark LaPedus, SemiMD senior editor

Amid record sales for the fourth quarter, Cymer Inc. disclosed that it has delayed the shipment of its 20 Watt extreme ultraviolet (EUV) power source upgrade unit by nearly a quarter.

The company also remains under pressure to deliver a separate 100 Watt power source for EUV by mid-year. The main EUV tool vendor — ASML Holding NV — expects to ship its NXE:3300B, a full-blown, 13.5nm EUV production tool, in the second half of 2012. Cymer is one of the EUV power source vendors for that tool.

For some time, Cymer has been shipping an EUV power source operating at 8 Watts, which is designed for ASML’s NXE:3100, a pre-production EUV machine. Cymer shipped three 8 Watt EUV power sources in the fourth quarter of 2011, which was ahead of schedule by a quarter.

However, the company was originally supposed to ship a 20 Watt upgrade for the NXE:3100 by the end of 2011 or the beginning of the first quarter of 2012. The unit, dubbed “Upgrade 1,” is said to have less than a 0.5 percent dose stability and a 90 percent duty cycle.

Now, Upgrade 1 will get shipped by the end of the first quarter, which represents a 1-to-2 month delay. “Upgrade 1 is behind schedule relative to our last call,” said Bob Akins, Cymer’s chief executive, during a conference call.

The Upgrade 1 unit was expected to be “accomplished by year end,” he said. Now, the upgrade will be shipped “before the end of the quarter. It won’t run at 20 Watts initially. By (the second quarter, it) will be at full power.”

In reality, the EUV power sources are far behind schedule. ASML says it is one or two years behind in EUV roadmap. “We are significantly behind our roadmap,” Akins said.

“Cymer has proven 20 Watts internally, but is only now in the process of getting qualified at ASML,” said C.J. Muse, an analyst with Barclays Capital, in a report. “Cymer remains confident that it can get it done, but it appears that instead of reaching this milestone by the end of 1Q ‘12, ASML will likely not qualify the laser until the April-May timeframe.

“The laser is at ASML today, and is in the process of getting qualified, and Cymer still expects this light source to be deployed to chipmakers some time in 1H ‘12. Here, the primary technical issue is duty cycle, where the main problems remain the thermal stability of the optics, gas stability of the laser and better control of the firing/timing of the laser/droplets,” Muse said.

In the meantime, Cymer and other EUV source vendors are developing separate power sources for ASML’s NXE:3300B. The tool is expected to have a throughput of 69 wafers an hour, which requires a 100 Watt power source.

Cymer expects to deliver that source on time and “in the summer of this year,” Akins said during the call. “That’s not without some risk. We are trying as hard as we can.”

“Cymer also discussed running parallel work in producing its (high volume manufacturing) source 2 for ASML’s 3300 tools,” Barclay’s Muse said. “On this front, Cymer remains optimistic it can meet the schedule previously discussed. So clearly some disappointment here — but we continue to believe Cymer will prove successful in its EUV light source effort, as we believe many of the challenges are more evolutionary than revolutionary.”

But to hedge its bets in case of EUV delays — and to prepare for the multi-patterning era — ASML has bolstered its 193nm immersion roadmap. As reported, the Dutch-based company is developing at least two more generations of its 193nm immersion tools, including a scanner designed to process 300 wafers an hour.

The semiconductor industry is currently transitioning to development and high-volume manufacturing of 20nm generation process devices, with the most critical layers exposed using 193nm immersion scanners and incorporating double patterning. “Lithography solutions that deliver ultra-high productivity and exceptional overlay accuracy are imperative to making double patterning cost effective,” said Hamid Zarringhalam, executive vice president of Nikon Precision Inc.

This week, Nikon announced that its NSR-S621D 193nm immersion scanner began shipping to IC manufacturers in January “for the most demanding immersion double patterning layers.” Nikon shipped the tools to its largest customer, reportedly Intel Corp.

The S621D makes use of its Streamlign Platform. The combination of Stream Alignment and Five-Eye FIA systems enables a throughput of 200 wafers per hour (125 exposure shots/wafer). In addition, the Bird’s Eye Control system uses interferometers in conjunction with encoders to deliver overlay accuracy ≤ 2 nm with optimal stability.

Meanwhile, for the fourth quarter of 2011, Cymer posted a net income of $12.5 million, equal to $0.40 per share, compared to net income of $32.9 million, equal to $1.08 per share in the fourth quarter of 2010 and net income of $11.3 million, equal to $0.36 per share, in the third quarter of 2011.

Revenue totaled $152.9 million, compared to revenue of $146.9 million in the fourth quarter of 2010, and revenue of $128.7 million in the third quarter of 2011. Cymer beat the consensus forecast for the quarter, which called for sales of $129 million and earnings of $0.23.

For the first quarter of 2012, revenue is expected to be approximately $138 million. Commenting on the outlook for the first quarter of 2012, Akins said: “We expect Installed base products revenue to remain at or above the prior quarter level led by installed base growth, increased ArF pulses and light source product enhancements. We anticipate shipping a similar number of DUV ArF Immersion light sources, as compared to last quarter, but a lower number of KrF. We also anticipate recognizing revenue on our fourth 3100 EUV source and our third TCZ system.”

With EUV orders pulled into 4Q, Cymer guided below analysts’ estimates for the first quarter. The consensus forecast is $0.31 a share on sales of $150 million for the first quarter.

 

[cbn]

After reading about those high throughputs for the latest ASML and Nikon 193nm immersion scanners (see post #22) I decided to look up some more information on EUV.

http://www.cymer.com/euv_light_sources/

Keeping Moore’s Law Alive In 1965, Intel co-founder Gordon Moore predicted that the number of transistors that can be placed onto a single IC would double approximately every eighteen months to two years, dictating what is now known in the industry as “Moore’s Law.” Each year, device manufacturers have achieved the advances predicted by Moore's Law, bringing about a next-generation chip to boost computing powers and memory storage capability - from computers and MP3 players to video games, home electronics and more. To keep pace with Moore’s Law in the rapidly advancing computer age, the semiconductor equipment industry has invested heavily in research and development on advanced alternatives to DUV lithography to keep the progress and economics of smaller faster electronic devices from slowing down.

To maintain the advancements of Moore’s Law, Cymer is leading the industry with its decade-long research and development of an extreme ultraviolet (EUV) lithography light source, the best viable long-term option for the continued creation of advanced semiconductor chips.

Today’s current-generation DUV lithography patterns circuitry at critical dimensions of ~250 nm to 45 nm, and is being used to develop next generation manufacturing processes of 32 nm. The shorter the wavelength, the more powerful the final integrated circuit - meaning smaller, faster, and more innovative electronic devices for mankind.

With EUV lithography, devices can be patterned from 32 nm to estimated single digit nm dimensions, keeping shrink progress and Moore's Law alive to enable future generations of electronic products. Due to the fact all matter absorbs EUV light, the lithography process must take place entirely in a vacuum, including all optical elements including the photomask.

The EUV light source operates by targeting a high power laser directed at droplets of tin (Sn), which when hit by the pulsed laser heats the fuel to create a plasma. This process spawned the common EUV industry term “laser-produced plasma,” or LPP, which refers to the source of the EUV system. (Though other techniques have been investigated such as discharge produced plasma (DPP), Cymer has implemented LPP as the most viable commercial EUV approach since 2004.)

Once the laser-produced plasma is created, a large collector mirror collects and focuses the 13.5 nm light. The EUV light is then delivered to the lithography system. As the light projects onto the mask, it is reflected onto a series of mirrors, which reduce the size of the image, and focus it onto a silicon wafer—similar to the way in which lenses in a camera use light to form images onto film or CCD chip.

The mirrors used by the EUV source are critical to the technology. The EUV source utilizes both concave and convex mirrors coated with several layers of molybdenum (Mo) and silicon (Si), in order to reflect the maximum possible amount of 13.5 nm EUV light. About thirty percent of the light is absorbed by each mirror. Without the coating, the light would be absorbed before reaching the wafer. Additionally, mirror surfaces must be nearly defect-free, as even the smallest imperfections can destroy the shape of the optics and distort the printed circuit pattern.

The lifetime of the collector mirror is a critical parameter in the development of LPP EUV sources. Deposition of target material as well as sputtering or implantation of incident particles can reduce the reflectivity of the mirror coating during exposure. Debris mitigation techniques are used to stop damage from occurring.

Probably the most important factor of an EUV lithography light source is the power at which it can continuously run. Cymer has developed techniques to increase the continuous power while running under typical operating conditions used for lithography applications. High-volume commercial production systems are expected to be required to operate at greater than 200W of power, 24 hours per day, in order to get the wafer throughput required by semiconductor device manufacturers.

The pilot light source in 2010 was the world’s first, commercial LPP EUV source for lithography applications, continuing Cymer’s legacy of leading the “light generation.”

First Diagram (in text) shows a 20KW CO2 laser located in the Fab sub-floor. This beam is transported to the Vacuum vessel (located within the scanner) by the beam transport and focusing system (which connects the laser in the subfloor to the vacuum vessel inside the scanner.) Once the beam gets to the Vacuum vessel it strikes a droplet of tin creating the EUV light. This EUV light is focused by the coated mirror and transported by a series of coated reflectors within the vacuum vessel to the wafer (about 2% of the light from the intermediate focus makes it to the wafer –see second diagram for this information).

Based on this (admittedly very simple understanding I have) it seems transmitting EUV light to the wafer isn't exactly the most efficient process at this time. (due to the high amount EUV light absorbed as it travels to the wafer) . With that said, creating the EUV light appears to be an even bigger challenge. According to this recent EE Times article Cymer is currently at only 30 watts for its EUV power source:

Cymer’s EUV light sources have for some time been exposing wafers at up to 11 Watts source power at customer facilities, resulting in NXE:3100 productivity of up to 7 wafers per hour. ASML and Cymer jointly made significant progress during the summer and have now proven in laboratories a sustained 30-Watt source exposure power potential, which would enable the NXE:3300B to expose 18 wafers per hour. ASML’s specified target remains at 105 Watts or 69 wafers per hour (wph), to be achieved for 2014 microchip production.

In contrast, the light sources for 193nm immersion are much more modest in their power outputs.....yet the quoted wafer throughput in post #22 is quite high. (see 60 to 90 watt power spec for Cymer's see link here for their XLR 600ix 193nm immersion double pattern light source. Maybe less light source power is needed due to the longer wavelength's lower absorption as it travels to wafer? Or maybe these advanced 193nm light sources are better in other ways besides power? Not sure.....but I am interested to see where all this will go. Maybe EUV will have a tough fight trying to overcome these advances occurring with 193nm immersion.

 

[Qianglong]

Man...all these sounds so fascinating! I just wonder what type of stable platform must these FABS be placed on as the node scales smaller. I mean the tiniest bit of movement will wreck the process and it gets even more so as things move down to 22nd and less...

 

[Idontcare]

Man...all these sounds so fascinating! I just wonder what type of stable platform must these FABS be placed on as the node scales smaller. I mean the tiniest bit of movement will wreck the process and it gets even more so as things move down to 22nd and less...

Even going all the way to the 0.5um (500nm) node, when we built fabs back then we would drive steel beams all the way through the ground surface until we hit bedrock.

For DMOS5 in Dallas (a texas instruments fab) we drove steel pilings >150ft straight down into the ground until we hit bedrock.

But the bedrock-moored steel beams are not for the fab, in fact they aren't even attached to the fab. The steel piling rises like a toothpick up through the earth and has a steel plate sitting on top (think of the head of a pin or the head of a nail) which is made to be level with the rest of the fab floor that is built around it (but a gap is maintained, so the fab vibrates and shifts all around the steel platform but never contacts it).

The litho tool is then placed on top of this steel platform (which itself might be all of 20ftx30ft in size).

So all the surface vibrations in the earth from cars and trucks and nearby building/road construction and so forth (stuff you and I never feel in bodies but is still there 24hrs a day) still goes to the fab and shakes it around the same as it shakes the nearby walmart or mcdonalds around, but the litho tools are vibrationally isolated from them.

Now the downside of being vibrationally coupled to the bedrock is that any deep seismic activities are then conducted up the steel piling.

When the Kobe earthquake struck Japan in 1995, our MIHO fabs in Japan got the living daylights shook out of them and afterwards we found their internal calibration targets had shifted by more than 6 inches (back then, typical miscalibration skew was on the order of 25-50um on a very bad day, to be off by inches was simply unheard of)