ASML buys Cymer (EUV tech stuff)

Discussion in 'CPUs and Overclocking' started by Lonyo, Oct 18, 2012.

  1. cbn

    cbn Lifer

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    More information on how EUV light is produced:

    http://www.eejournal.com/archives/articles/20120302_uav/

    NOTE: LPP (in the text below) stands for "Laser Produced Plasma", Cymer has a description with pictures here.

     
  2. khon

    khon Golden Member

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    It's not the exposure time that matters, but yes it is basically the same for each pass, though the pattern won't be.

    However, quadruple patterning is not as simple as exposing the same wafer four times in a row. In between each exposure you have to do multiple other processes (spacer deposition, chemical/thermal freeze or reactive ion etching depending on which multiple exposure technique you use). Extra patterning steps means higher costs.

    Also, you have to keep in mind that with each step you have to go through, there will always be some defects added. So if you have to pattern the same layer four times rather than two, you will inevitably have a lower yield. Thus you end up putting in twice as much work, and getting less working product out.
     
    #27 khon, Oct 28, 2012
    Last edited: Oct 28, 2012
  3. khon

    khon Golden Member

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    That is correct.

    The fundamental difference between EUV and DUV, is that there are many material that have excellent transparency for DUV, but no material at all that have good transparency for EUV. That's why EUV has to use mirrors instead of lenses, and it's why the inside of the scanner has to be near vacuum conditions. But even with these precautions, the vast majority of the EUV light is lost before it ever reaches the wafer.

    EUV and DUV resists require roughly the same dose, so in order to get that, EUV lasers must be far more powerful.
     
  4. cbn

    cbn Lifer

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    I didn't think about that.....thank you for pointing this out!

    So just to keep the defects per wafer the same on the new node the Scanner would need to have double the accuracy/precision as the scanner used on the old node.

    I noticed in the below link prices per wafer are really jumping (from 25% increase per node to 60%+) starting at 20nm

    http://semimd.com/mentor/2011/06/01/double-patterning-sharing-the-benefit-and-the-burden/

    [​IMG]

    Furthermore, according to the quote below (from the linked article), costs on the design side will also increase due to the use of multi-patterning.

    Combine these increased costs (Fab and extra design side software/work) with the possibility of reduced yields and I can see why Fabs would want to reduce the number of extra patterns needed per wafer.
     
    #29 cbn, Oct 28, 2012
    Last edited: Oct 28, 2012
  5. Idontcare

    Idontcare Elite Member

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    (1) When it comes to anything pertaining to prices, alway be wary of the date of the pricing source in question - this one is nearly 18 months old.

    (2) When it comes to anything pertaining to prices on process nodes that are not yet in production, always be wary of the reality of over-hyped pricing that never enters into reality but makes for great sexy articles in the trade journals. Think about Intel's tray pricing for 1000k units...no one ever pays Intel that price in reality, they always pay something much less.

    (3) On the matter of that specific graph, something is afoot because 65nm foundry wafers cost $2.1k/wfr all the way back in 2007 when they were at their priciest...I imagine they are now down to ~$1300/wfr, if not even lower...so I'd question the numerical accuracy (and hence relevance) of the other numbers in the graph as well.

    When it comes to forecasting price per wafer on future nodes the graph above is kind of like the once and forever doomsday "brick wall of escalating costs" that get bandied about every node but then fails to materialize in reality once the contracts are finalized and the node goes into production.

    Where wafer prices really start rising is when you include IC design costs into the per-wafer cost (so not the cost to manufacture the wafer, but the cost to the fabless company of designing the IC for the wafers plus the cost of producing the wafers) when the fabless company in question is simultaneously looking at low-volume runs of their IC. In those scenarios the price-per-wafer blows up at smaller nodes not for the manufacturing costs per se but for the mask-set cost which is a fixed expense (more or less) much like the fixed expense of designing the IC itself.
     
  6. Ajay

    Ajay Platinum Member

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    Thanks for all the posts ComputerBotttleneck!

    Some of these companies must have old info on their websites. I find it hard to believe that the reflectivity of EUV is ~70%. 70% was state of the art for EUV/Near X-Ray wavelengths about 15 years ago! Though, there must be some reason that EUV light sources are too dim to allow high speed exposures. Maybe what was state of the art in the late 90's is just becoming affordable :(
     
  7. khon

    khon Golden Member

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    It's not old info, ~70% is the current state of the art.
     
  8. Ajay

    Ajay Platinum Member

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  9. Idontcare

    Idontcare Elite Member

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    Wow, no wonder EUV is so delayed, progress in terms of the leading-edge of capability has been rather abysmal it would appear.

    It is interesting that the power of the light source is a gating factor.

    You know what I did in my family room when one light bulb wasn't providing enough light for illuminating the room? I brought in a second lamp.

    Turns out that the light output from multiple lightbulbs is additive ;)

    Someday, maybe, state of the art in EUV illumination will catch up with the state of the art illumination techniques I use in my family room :D :p
     
  10. cbn

    cbn Lifer

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    According to this article Cymer is able to get the power (At the IF-intermediate focus) up to 160 watts with a larger 28KW laser and pre-pulse in the lab.....but they just can't sustain it.

    Not sure about all the factors holding back improvements in duty cycle at high wattage, But I do see "tin droplet debris" (produced after the laser hits the tin droplet mentioned) several times in the following quotes from the above linked article.

    Now if we look back to the third quote from post # 26 of this thread, Cymer has mentioned tin droplet debris can reduce Clarity and thus efficiency of the collector. More tin debris on collector.....less power at Intermediate focus (where power is measured for these light sources.)

    Therefore it appears to me one factor holding back duty cycle times at high wattage involves getting the laser and pre-pulse more accurately pointed at the tin droplet.

    More accurate and consistent placement of the pre-pulse and laser on the tin droplet *should* result in a more predictable and controlled tin debris scattering.

    Less debris accumulating on collector = more EUV collected at IF (where the power level of these light sources is measured) for a longer period of time. (ie, higher duty cycle time)
     
  11. cbn

    cbn Lifer

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    http://chipdesignmag.com/display.php?articleId=5190

    According to the above article 80% reflectivity (for 6.7nm EUV) is theoretically possible.

    Although the 80% is mentioned for 6.7nm EUV (and very well may be specific to 6.7nm) , I would think having greater reflectivity should also help with 13.5nm EUV power transmission in situations where a greater numbers of mirrors are needed for the "projection lens" (ie, getting full field imaging at a higher Numerical apeture). Like the quote above mentions increasing mirrors (with 70% reflectivity) from six to eight reduces EUV power transmission to the wafer by half.

    Either that, or EUV source power (measured at the IF) would have to double for a 8 mirror projection lens high resolution set-up.

    According to this article ASML does have plans for higher NA (using 8 mirrors for full field imaging) for 13.5nm EUV wavelength allowing a resolution of 11nm for the tool.

    [​IMG]

    See the 6/8 Mirror set-up "under study" (shaded in blue) for >.40 NA allowing a resolution of 11nm for the 13.5nm wavelength EUV and a resolution <8nm for the 6.7nm wavelength EUV.
     
    #36 cbn, Nov 1, 2012
    Last edited: Nov 1, 2012
  12. Ajay

    Ajay Platinum Member

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    So the biggest obstacle for EUVL seems to be the droplet generator. That makes sense for it sure does seem to be an intrinsically difficult process. Thanks for all the research you done BN!
     
  13. cbn

    cbn Lifer

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    Looking through some EUV source research (as a lay person trying to find his way through this extremely complicated area) it appears computer simulation might be a way to speed the development of EUV source.

    In particular one group in this conference--> http://spie.org/app/program/index.c...&conference_id=1039349&event_id=996835&list=1 has published quite a bit on the topic. (NOTE: some of their past papers are available free on the internet)

    Here is their upcoming paper for the 2013 SPIE conference.

    One of their fairly recent past papers (from 2009)---> https://engineering.purdue.edu/CMUXE/Publications/Valeryi/SPIE09AH.pdf (in which they mention the newly built lab they use to compare simulation data to actual LPP source production vs. debris accumuation on the collector.)

    But how long will such research (such as this and others) take to put into production?

    I am not sure, but I was encouraged when I saw the following---> http://www.uh.edu/~lcr3600/simulation/historical.html

     
  14. Idontcare

    Idontcare Elite Member

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    Intel has really been aggressively using what they refer to as Computational Lithography for mask optimization and it naturally extends into the EUV regime.

    There are some really impressive images out there (let me know if you aren't having any luck finding them) comparing the image fidelity that is enabled with computational litho versus traditional mask optimization.

    See these for examples:
    www2.hust.edu.cn/nom/papers/2011_IEEE_NEMS_1.pdf
    and...er just click through the links from this google search (the "Why computational lithography" link 4th down is awesome, check it out :))
     
  15. soccerballtux

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    woohoo this thread delivers! 70% through 13 mirrors -> 2% light from original Laser, 150ft steel beams to the rock underneath the fab!

    Wonder how much longer until we should start shorting Intel...
     
  16. cbn

    cbn Lifer

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    Thanks for the links IDC.

    Here are some images from that "Why computational lithography" PDF found in the google search you provided--> http://archive.lithoworkshop.org/pdfs/conference/2009/Yuri Granik.pdf

    [​IMG]

    [​IMG]

    [​IMG]

    [​IMG]

    According to the "Why Computational Lithography" PDF the above four images (going from top to bottom) are four steps in a particular type of source optimization.

    Speaking of source optimization, I found the following two examples of Computational lithography (Source Mask Optimization vs Optical proximity correction) interesting:

    [​IMG]

    [​IMG]

    Notice in the last image (directly above) labelled "Source-Mask Optimzation (SMO)" it is mentioned the single exposure mask is optimized for the illumination pattern (aka the complex optimized illumination source) rather than being constrained to the target shape topology.

    Now compare this to the image labelled "Traditional Computational Lithography applied to 22nm". Notice it says "double exposure masks modified by Optical Proximity correction". This computational lithography uses a much more simple dipole illumination source pattern.

    The major difference (to me) appears that the more complex "Source and mask optimized" computational lithography is "co-optimized" to a greater degree compared to the OPC (mask level) Computational lithography with its simpler light illumination pattern.

    More information on combining different shaped light sources and masks together on page 8 of this 2008 ASML PDF ---> http://www.asml.com/doclib/press/pr...015_Break_out_4_Computational_Lithography.pdf

    [​IMG]
     
    #41 cbn, Nov 2, 2012
    Last edited: Nov 3, 2012
  17. Qianglong

    Qianglong Senior member

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    Wow..thanks for the info! Very fascinating. I always wondered what type of special precations TSMC fabs have to protect themselves against the frequent earthquakes in TW. I guess the fab buildings are designed to compensate for certain magnitude of earthquake before the tremors botches the machines?
     
  18. Idontcare

    Idontcare Elite Member

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    They do, think about the hard-drive in your laptop. The heads and the arms auto-park themselves on the fly in response to detected movement that is predicted to become problematic.

    The instant you grab the laptop from the side and begin to lift it for example, heads get parked because the drive is designed to expect even worse gyrations are to come before it gets better, then it gives the heads the all-clear signal and they come back out to resume data operations.

    Fabs are equipped with that kind of idea when it comes to parking tools and so forth based on seismic detection and prediction models.

    It sounds fancy and high-tech but really its not considering that even your $60 bare-bones laptop drive sports the tech to make it happen, so your multi-billion dollar fabs do to.

    But just like the case with the hard-drive that still dies when you drop your laptop onto the sidewalk, earthquakes still destroy the equipment in a fab when the epicenter is too close.