coercitiv
Diamond Member
We don't even know if ADL uses Foveros anywhere in the product stack.
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[Ashraf] 10nm "Lakefield" SoC with Intel big + little cores
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IntelUser2000
Elite Member
You are right. But when its aimed at such low clocks they can use different transistors to lower leakage. The -U parts are tuned for lower leakage for low idle operation, but use more power at higher frequencies compared to -H and -S.
The point is they are flexible enough to have a separate die, which allows for further optimization such as cutting down the memory width and PCI Express lanes. Atom for example had 6 different die iterations at one point and their volume and ASPs were a mere fraction.
coercitiv
Diamond Member
As you already pointed out, Lakefield came with a number of restrictions such as die area, power, PCB size. ADL may be able to match some restictions, for example power, but to meet them all it would need same manufacturing tricks as Lakefield, at which point it would effectively be a Lakefield class product.
Where the hell did you get that?
ST Integer score 2706 vs. 2036
MEDION E2294 MD62700 - Geekbench
Benchmark results for a MEDION E2294 MD62700 with an Intel Pentium Silver N5000 processor.browser.geekbench.com
Acer TravelMate Spin B118-R - Geekbench
Benchmark results for an Acer TravelMate Spin B118-R with an Intel Pentium N4200 processor.
Cinebench ST/MT: 35%
Acer Swift 1 SF114-32 (N5000, SSD, FHD) Laptop Review
We test the Acer Swift 1 SF114-32 equipped with a Pentium Silver N5000 CPU, Solid State Disk, and Full HD display. How does the 14-inch notebook fare compared to the competition?www.notebookcheck.net
The Intel Atom Thread
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You were talking about IPC before. Clock speed generally accounts for the rest.
Same clockspeed from Cinebench:
Cinebench R15 1T
N4100 2.4 Ghz (Goldmont Plus) 70
N3350 2.4 Ghz (Goldmont) 48
Roland00Address
Platinum Member
Does some math...
48 * 1.46 = 70.08
45% to 46% faster that is not those numbers I seen earlier with 30% or maybe only 15%.
Sigh I want new hardware and with new hardware I want to recapture excitement for intel has been so meh for the last 4 to 7 years (depends on what excites you), I see things that interest me but who knows if it will ever come out in large quantities at prices I appreciate.
vigilant007
Junior Member
I think stopping development of the Atom when they did was the bad decision. Having a 30% increase year over year I’d say is pretty good. But considering they stopped development a while ago, things could be in much better shape, and comparable to what we are seeing from the ARM side.
30% for a year over year update is actually great. But compared to how long it took to get the update considering they stopped development we could have had better compared to that same time if it was still being continually developed.
The jump to OoOE was a very nice bump in performance. I remember getting my girlfriend a new Netbook when that came out because the original one I got here was so miserable to use at the time. (Yes, I got my girlfriend a Netbook. She didn’t have a computer, and at the time it was a “fancy” gift for that point in my life)
IntelUser2000
Elite Member
They were better than the regular ARM parts with Silvermont. If they updated it every year it would have been much better. But the next year's Airmont didn't advance, and Goldmont took more than a year to come out.
At least they'll pick up the pace with Tremont and Gracemont. Gracemont should come end of next year with Alderlake parts.
The OoOE Silvermont was twice as fast when you consider the clock speed increase too. I bought a Tablet based on the predecessor and I could tell it was slow. The Silvermont based Tablet I got for myself was very usable.
vigilant007
Junior Member
I hope you are right, and I REALLY hope the Surface Neo gets a variant that includes it.
I had a lot of hope for Atom when it was released. Especially for Android Phones and Tablets. Why? Competition works! Netbooks existed because they weren’t great, but for many people it was a “workable” way to surf the web. Some people, thats literally all they do.
IntelUser2000
Elite Member
Surface Neo is Lakefield, unless they want to delay further to squeeze Lakefield-R in, but even then its unlikely without serious delays. For whatever reason they are taking sweet time releasing the platforms based on the chip, even though they tell us its ready. Let's say they speed it up by 3 months, then we can expect Lakefield-R products by March-April 2021 timeframe with Xe graphics and the 10nm SF process.
I don't believe we'll see Gracemont in Lakefield-based products until after Lakefield-R.
I quickly lost hope on Android phones/tablets. They are not playing on level ground but needs a binary translator which sacrifices not only performance but compatibility. I've seen quite a few user reviews saying it'll feel fast until its suddenly jerky. If it was 5x as fast then it would gain adoption but that's impossible.
This is why we'll continue to have the x86/Windows, Android/ARM divide.
The problem with Atom is that it had no market at the prices Intel needed to sell it at to make desktop equivalent margins, and it couldn't justify devoting leading edge wafers at the prices Intel was forced to sell it at to compete with Qualcomm SoCs. Not to mention the fact that Intel struggled to make modems competitive with Qualcomm's.
If being x86 had been an advantage on mobile Intel might have had a chance. Intel has never been able to succeed in a market where they couldn't leverage their x86 monopoly, they certainly weren't ever going to win a fight where they had to come from behind due to the added disadvantage of the modem and not being able to leverage their (at the time) process advantage.
Had they continued development of Atom they would have had faster cores, sure, but it still wouldn't succeed in the market using a trailing edge process. Especially in 2020, when Intel's leading edge becomes everyone else's trailing edge once TSMC N5 based products begin their roll out next month.
vigilant007
Junior Member
Want to hit on both points adequately. Surface Neo has been delayed because Windows 10x isn’t ready yet. I’m kinda thinking because they don’t have adoption at a useful level for the way they want applications to be packaged.
On the issues with Android, that has multiple problems. The original runtime wasn’t great. The issues that many people saw, including you were felt by everyone, and it’s my understanding the new runtime runs better. I can’t speak to that directly, to that.
coercitiv
Diamond Member
Qualcomm doubles down with 8cx Gen 2... and they argue Lakefield has lower perf/watt than Intel's 10th gen U parts. Seem to me 2020 is plagued with all kinds of weird.
Grain if salt since it is Samsung presenting the data, obviously. Not sure about the core vs hybrid for Intel. Point of Lakefield was to lower idle and standby power, was it not? So the result could depend on the test and the workload. Very confusing graphs BTW. It is early in the morning here, but it took me a while to figure out why a shorter bar had a positive change.
IntelUser2000
Elite Member
Can't say much about the 8cx comparisons, other than that they were using cherry-picked benchmarks last year.
The problem is Lakefield. I honestly expected the battery life comparison to be better. It doesn't seem to be any better than the Amberlake-Y devices. Then again, we have a single design for comparison so what do we know!?
I should have guessed based on the design wins(or lack thereof). Two this year, and barely should have been a big red flag. Same seems to be an issue with Lakefield-R. They really need to reduce the gap from regular Core, because it'll be a generation behind again.
If Tigerlake devices get decent battery life increases, then we know process is part of the problem with Lakefield. What else?
The problem is Lakefield. I honestly expected the battery life comparison to be better. It doesn't seem to be any better than the Amberlake-Y devices. Then again, we have a single design for comparison so what do we know!?
I should have guessed based on the design wins(or lack thereof). Two this year, and barely should have been a big red flag. Same seems to be an issue with Lakefield-R. They really need to reduce the gap from regular Core, because it'll be a generation behind again.
If Tigerlake devices get decent battery life increases, then we know process is part of the problem with Lakefield. What else?
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coercitiv
Diamond Member
Intel wants it all: small die, low power, high margins. That's why Qualcomm can turn around and point out the obvious weak spots in their platform, like the fact that a quad Cove chip may match or even beat Lakefield's 1+4 configuration under specific workloads. I suspect they did this using some throughput oriented benchmark while measuring the energy usage of the entire system. This way the i5 had both a die area advantage and also a beefy bonus from completing the work early. As I said before, in my book the base building block for Lakefield should be 2 big cores. After that they can add 4-6 small cores to boost MT perf while getting the benefits of low idle power usage.
I expect the 4c/8t TGL @ 7W TDP will walk all over Lakefield. That leaves the hibrid chip with experimental devices that require very small PCBs or very thin bodies. So it turns out that small die + low power + high margins leads to... low volumes.
On the flip side Alder Lake stays with 2 big cores minimum, so that one should be a sane config even when going sub 10W.
I expect the 4c/8t TGL @ 7W TDP will walk all over Lakefield. That leaves the hibrid chip with experimental devices that require very small PCBs or very thin bodies. So it turns out that small die + low power + high margins leads to... low volumes.
On the flip side Alder Lake stays with 2 big cores minimum, so that one should be a sane config even when going sub 10W.
Well it is still the Cortex A76 based platform from 2 years ago. For this however we have benchmarks which pretty confirm the graphs above. For multithreaded workloads a Microsoft or Samsung device using the 8XC is between 50-90% faster than Lakefield - so the 51% number is already conservative.
Alder Lake is an LGA-socket platform - interchangeable chips mostly for desktops.
Lakefield is a platform for small, thin mobile devices.
Both are hybrid chips but that's where similarities end.
Alder Lake isn't just desktop chips.
I have no idea where you're from, but do they teach the word "mostly" there? 🙂
Anyway, isn't the LGA1700 desktop lineup the only confirmed Alder Lake at this point?
LightningZ71
Platinum Member
I'm beginning to think that Intel is going about this the wrong way due to their own internal bias towards believing that their process tech is just miles better than anyone else.
One of the things I keep coming back to is that Intel seems loathe to customize any of their process tech solutions towards a balance of maximum power efficiency and overall compactness. As we have seen with almost every mobile arm solution out there, each process node and design rules set that they use optimizes for power and density first, then tries to squeeze out as much performance as it can afterwards. For Intel's lakefield, it looks like they are just using their same process for 10+ that they used with Ice Lake. If that's the case, of course they're going to trail custom mobile SoCs that have been targeting that market for generations.
I think that Intel really should be planning for using a two stack of compute dies, with the lower stack item being their best atom core design possible on a process set that is aimed as much at efficiency as possible, with a performance optimized die above it that has a pair of Sunny Cove or later big cores with a closely coupled cache. Memory and gpu can be stacked on top of that.
If you want maximum performance, you want to light up those cores and burn away as quickly as possible so that you can shut them down again in a hurry. You can tool around in low power mode on the atom cores on a power optimized die while sipping power.
This is where their stacking tech could show its power. But, Intel needs to have a set of design rules for 10sf that are power optimized first.
One of the things I keep coming back to is that Intel seems loathe to customize any of their process tech solutions towards a balance of maximum power efficiency and overall compactness. As we have seen with almost every mobile arm solution out there, each process node and design rules set that they use optimizes for power and density first, then tries to squeeze out as much performance as it can afterwards. For Intel's lakefield, it looks like they are just using their same process for 10+ that they used with Ice Lake. If that's the case, of course they're going to trail custom mobile SoCs that have been targeting that market for generations.
I think that Intel really should be planning for using a two stack of compute dies, with the lower stack item being their best atom core design possible on a process set that is aimed as much at efficiency as possible, with a performance optimized die above it that has a pair of Sunny Cove or later big cores with a closely coupled cache. Memory and gpu can be stacked on top of that.
If you want maximum performance, you want to light up those cores and burn away as quickly as possible so that you can shut them down again in a hurry. You can tool around in low power mode on the atom cores on a power optimized die while sipping power.
This is where their stacking tech could show its power. But, Intel needs to have a set of design rules for 10sf that are power optimized first.
Alder Lake mobile wouldn't be LGA, so "mostly" still doesn't apply.
And no specific Alder Lake is confirmed, but Sharkbay has leaked an entire lineup.
coercitiv
Diamond Member
Because that's a tradeoff you are forced to make. If you want higher performance you use high performance transistors, but those use more power and more area. Intel could use lower power transistors and "optimize for power and density first" but they'd have to pay for that choice by reaching a bit lower max clock rate.
The tradeoff is obvious for ARM designs which are almost entirely used in mobile (or smaller) devices where power draw is paramount. It is just a happy coincidence that optimizing for low power also optimizes for density. There would be some more interesting friction for phone OEMs in the choice between low cost and low power if lower power implied lower density instead.
I don't know the degree to which the process itself (rather than the parameters you tweak in e.g. the transistors / cell libraries) can be slanted one way or another. Probably not much, given how flexible TSMC's recent processes appear to be. If you think Intel is choosing incorrectly, they aren't necessarily choosing wrong when designing their processes, but rather when they are choosing the parameters to fab a given design.
Intel has competed on performance for decades, they are very comfortable doing that so it is no surprise it continues to this day. They've never really competed on power - as far as low power goes their marketing only does comparisons with Intel's previous generations. What AMD is doing power wise doesn't matter to them, and ARM is totally irrelevant to their market. In the PC world consumers mostly don't care - they buy a laptop for x number of hours of battery life, not 15W TDP. As far as laptop buyers are concerned, it is the OEM's problem to figure out how big of a battery is needed for whatever Intel spits out.
IntelUser2000
Elite Member
Tremont is very compact. It's a quarter the size of Sunny Cove. Actually if you isolate it to only the core, its 5x the difference. It's their Core cores that are so large, due to aiming at everything from 5W CPUs to 5GHz+ desktop chips.
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