[Ashraf] 10nm "Lakefield" SoC with Intel big + little cores

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IntelUser2000

Elite Member
Oct 14, 2003
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One thing I don't really understand. Why going big little style? Let's say for hypothetical 1 big 1 little core compared to a dual core of the same architecture CPU with 1 core with transistors optimized for let's say 1.6 GHz max frequency and 1 core with transistors that can run up to 4 GHz? Is the power savings gained from in order architecture that much compared to out of order architecture?
Tremont is not in-order. They moved to out of order in 2013. It's a fairly wide architecture with performance similar to Ivy Bridge.

The way you are suggesting would result in crap multi-threaded performance. Lakefield has 4 Tremont cores for that.

Also the quad Tremont core cluster takes up roughly the same size as a single Sunny Cove core.

How much I/O is integrated into Lakefield that is not in Renoir, but rather in a separate southbridge chip?
I don't know about I/O, they might be similar since Renoir has integrated PCH functions. But Lakefield also has PoP memory which has to be part of TDP and will take up at least 1W.
 

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