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Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion

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ARM Community Site
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Soon it will be useful beyond Geekbench scores.
“The SME2-enhanced performance in your applications will then be portable across Arm-based platforms from iOS and iPadOS to MacOS and Android.”

IMG_2254.png
 
Io Magnesso said:
In the first place, it is called an accelerator or a coprocessor that is shared.
It's strange that the SME is used for single-thread benchmarks.
Click to expand...

That's how Apple implemented it, but nothing says ARM will do the same. In fact, I think it is unlikely they would do that, because they design CORES not SoCs so designing SME as something separate from the core would be a sea change in the way they do things. Not saying it is impossible, but SME2 is defined in the ARMv9 ISA as specific instructions just like SVE. Just like AVX512 - which could be implemented in the way Apple implemented SME if AMD or Intel had chosen to. They just don't have any experience doing anything like that since the 386 days when the FPU was available as a separate co-processor chip.
 
I thought M4 support SME only. Any other source mention that M4 supporting SME2 beside today announcement???

SME2 is part of ARMv9.4 and from the Wiki M4 uses ARMv9.2
 
Tigerick said:
I thought M4 support SME only. Any other source mention that M4 supporting SME2 beside today announcement???

SME2 is part of ARMv9.4 and from the Wiki M4 uses ARMv9.2
Click to expand...
Apples own docs say sme2 support is available. As well Geekbench reports sm2 in the logs.
 
Doug S said:
That's how Apple implemented it, but nothing says ARM will do the same. In fact, I think it is unlikely they would do that, because they design CORES not SoCs so designing SME as something separate from the core would be a sea change in the way they do things. Not saying it is impossible, but SME2 is defined in the ARMv9 ISA as specific instructions just like SVE. Just like AVX512 - which could be implemented in the way Apple implemented SME if AMD or Intel had chosen to. They just don't have any experience doing anything like that since the 386 days when the FPU was available as a separate co-processor chip.
Click to expand...
I know what you mean
Apple shares SME units across multiple cores, like an accelerator (coprocessor)
Apple has implemented it that way, but we still don't know how other ARMs will implement it.
 
Tigerick said:
I thought M4 support SME only. Any other source mention that M4 supporting SME2 beside today announcement???

SME2 is part of ARMv9.4 and from the Wiki M4 uses ARMv9.2
Click to expand...

SME is defined in ARMv9.2, SME2 is defined in ARMv9.3, SME2p1 is defined in ARMv9.4, a bunch of specific named additions to SME (shades of the Intel confusion around AVX512 🙄 ) are defined in ARMv9.5, and SME2p2 is defined in ARMv9.6.

Apple's M4 patches to LLVM/clang define it as ARMv8.7. I think I remember seeing claims there was something that's mandatory in ARMv9 that Apple hasn't implemented so they can't call it ARMv9 - maybe that's SVE but I'm 99% sure that SVE isn't strictly required in ARMv9. Now of course SME2 is not part of any ARMv8 iteration, but supporting MORE than the spec requires isn't really a problem I suppose.
 
Doug S said:
SME is defined in ARMv9.2, SME2 is defined in ARMv9.3, SME2p1 is defined in ARMv9.4, a bunch of specific named additions to SME (shades of the Intel confusion around AVX512 🙄 ) are defined in ARMv9.5, and SME2p2 is defined in ARMv9.6.

Apple's M4 patches to LLVM/clang define it as ARMv8.7. I think I remember seeing claims there was something that's mandatory in ARMv9 that Apple hasn't implemented so they can't call it ARMv9 - maybe that's SVE but I'm 99% sure that SVE isn't strictly required in ARMv9. Now of course SME2 is not part of any ARMv8 iteration, but supporting MORE than the spec requires isn't really a problem I suppose.
Click to expand...
It's a hassle... AVX512 is also mostly
 
Doug S said:
SME is defined in ARMv9.2, SME2 is defined in ARMv9.3, SME2p1 is defined in ARMv9.4, a bunch of specific named additions to SME (shades of the Intel confusion around AVX512 🙄 ) are defined in ARMv9.5, and SME2p2 is defined in ARMv9.6.

Apple's M4 patches to LLVM/clang define it as ARMv8.7. I think I remember seeing claims there was something that's mandatory in ARMv9 that Apple hasn't implemented so they can't call it ARMv9 - maybe that's SVE but I'm 99% sure that SVE isn't strictly required in ARMv9. Now of course SME2 is not part of any ARMv8 iteration, but supporting MORE than the spec requires isn't really a problem I suppose.
Click to expand...
Damn confusing. Guess my table is not comprehensive enough for all versions of SME 😳

ARM-Version.png
 
Tigerick said:
Damn confusing. Guess my table is not comprehensive enough for all versions of SME 😳

View attachment 126988
Click to expand...

That table is wrong. ARM's own site clearly shows ARMv9.3 is where SME2 was defined:

https://developer.arm.com/documenta...scriptions/The-Armv9-3-architecture-extension

It also has links to all the ARMv8 and ARMv9 extensions to see what was added when.

EDIT: if you look at the ARMv9.2 tab at the very bottom it lists a bunch of optional features added in later releases of ARMv9.2. One of them is SME2p1 (i.e. the version of SME defined in ARMv9.4)
 
Last edited:
poke01 said:
Apples M4 core is v9.2A. It’s in their cpu optimisation guide
Click to expand...

It was originally defined as ARMv8.7 in LLVM. I dug up the patch Apple submitted for that, it shows why:

+ // Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as
+ // requiring SVE, which is optional according to the Arm ARM and not
+ // supported by the core. ARMv8.7a is the next closest choice.
Click to expand...
 
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