Discussion ARM Cortex/Neoverse IP + SoCs (no custom cores) Discussion

[soresu]

It seems to be an academic event sponsored by ARM.

Yes they seem to get around a bit, probably a necessity given they make their money by IP rather than physical product.

 

[poke01]

Get Ready for Arm SME: Coming Soon to Android

Build next-gen mobile AI apps with SME2—no code changes needed. Accelerate performance across devices using top AI frameworks and runtimes.

community.arm.com

Soon it will be useful beyond Geekbench scores.
“The SME2-enhanced performance in your applications will then be portable across Arm-based platforms from iOS and iPadOS to MacOS and Android.”

 

[soresu]

Get Ready for Arm SME: Coming Soon to Android

Build next-gen mobile AI apps with SME2—no code changes needed. Accelerate performance across devices using top AI frameworks and runtimes.

community.arm.com

Soon it will be useful beyond Geekbench scores.
“The SME2-enhanced performance in your applications will then be portable across Arm-based platforms from iOS and iPadOS to MacOS and Android.”

View attachment 126940

Oh good, jumping straight to SME2.

 

[soresu]

This might be when they announce...

Arm Announces Earnings Release Date for First Quarter Fiscal Year Ended 2026

Arm (NASDAQ:ARM) will report financial results for the first quarter of fiscal year 2026 on July 30, 2025 after market close.

newsroom.arm.com

 

[Doug S]

Oh good, jumping straight to SME2.

SME2 is what M4/A18 currently support and was introduced by ARM in 2022. Not sure why ARM is hyping it now, other than because "AI".

 

[poke01]

SME2 is what M4/A18 currently support and was introduced by ARM in 2022. Not sure why ARM is hyping it now, other than because "AI".

They are hyping it now cause it will finally be supported by ARMs cores this year.

 

[MS_AT]

Arm-based platforms from iOS and iPadOS to MacOS and Android.”

but not Windows? Curious.

 

[Io Magnesso]

They are hyping it now cause it will finally be supported by ARMs cores this year.

In the first place, it is called an accelerator or a coprocessor that is shared.
It's strange that the SME is used for single-thread benchmarks.

 

[Io Magnesso]

In the first place, it is called an accelerator or a coprocessor that is shared.
It's strange that the SME is used for single-thread benchmarks.

That's what is said to be the bulk of the score.
I'm not saying that SME is bad, it's a complaint about the Geekbench.

 

[Io Magnesso]

That's what is said to be the bulk of the score.
I'm not saying that SME is bad, it's a complaint about the Geekbench.

If so, I think it would be good to increase the percentage of the score to AVX512 as well...
It's kind of unfair...

 

[Doug S]

In the first place, it is called an accelerator or a coprocessor that is shared.
It's strange that the SME is used for single-thread benchmarks.

That's how Apple implemented it, but nothing says ARM will do the same. In fact, I think it is unlikely they would do that, because they design CORES not SoCs so designing SME as something separate from the core would be a sea change in the way they do things. Not saying it is impossible, but SME2 is defined in the ARMv9 ISA as specific instructions just like SVE. Just like AVX512 - which could be implemented in the way Apple implemented SME if AMD or Intel had chosen to. They just don't have any experience doing anything like that since the 386 days when the FPU was available as a separate co-processor chip.

 

[Tigerick]

I thought M4 support SME only. Any other source mention that M4 supporting SME2 beside today announcement???

SME2 is part of ARMv9.4 and from the Wiki M4 uses ARMv9.2

 

[poke01]

I thought M4 support SME only. Any other source mention that M4 supporting SME2 beside today announcement???

SME2 is part of ARMv9.4 and from the Wiki M4 uses ARMv9.2

Apples own docs say sme2 support is available. As well Geekbench reports sm2 in the logs.

 

[Io Magnesso]

That's how Apple implemented it, but nothing says ARM will do the same. In fact, I think it is unlikely they would do that, because they design CORES not SoCs so designing SME as something separate from the core would be a sea change in the way they do things. Not saying it is impossible, but SME2 is defined in the ARMv9 ISA as specific instructions just like SVE. Just like AVX512 - which could be implemented in the way Apple implemented SME if AMD or Intel had chosen to. They just don't have any experience doing anything like that since the 386 days when the FPU was available as a separate co-processor chip.

I know what you mean
Apple shares SME units across multiple cores, like an accelerator (coprocessor)
Apple has implemented it that way, but we still don't know how other ARMs will implement it.

 

[Doug S]

I thought M4 support SME only. Any other source mention that M4 supporting SME2 beside today announcement???

SME2 is part of ARMv9.4 and from the Wiki M4 uses ARMv9.2

SME is defined in ARMv9.2, SME2 is defined in ARMv9.3, SME2p1 is defined in ARMv9.4, a bunch of specific named additions to SME (shades of the Intel confusion around AVX512 ) are defined in ARMv9.5, and SME2p2 is defined in ARMv9.6.

Apple's M4 patches to LLVM/clang define it as ARMv8.7. I think I remember seeing claims there was something that's mandatory in ARMv9 that Apple hasn't implemented so they can't call it ARMv9 - maybe that's SVE but I'm 99% sure that SVE isn't strictly required in ARMv9. Now of course SME2 is not part of any ARMv8 iteration, but supporting MORE than the spec requires isn't really a problem I suppose.

 

[Io Magnesso]

SME is defined in ARMv9.2, SME2 is defined in ARMv9.3, SME2p1 is defined in ARMv9.4, a bunch of specific named additions to SME (shades of the Intel confusion around AVX512 ) are defined in ARMv9.5, and SME2p2 is defined in ARMv9.6.

Apple's M4 patches to LLVM/clang define it as ARMv8.7. I think I remember seeing claims there was something that's mandatory in ARMv9 that Apple hasn't implemented so they can't call it ARMv9 - maybe that's SVE but I'm 99% sure that SVE isn't strictly required in ARMv9. Now of course SME2 is not part of any ARMv8 iteration, but supporting MORE than the spec requires isn't really a problem I suppose.

It's a hassle... AVX512 is also mostly

 

[Tigerick]

SME is defined in ARMv9.2, SME2 is defined in ARMv9.3, SME2p1 is defined in ARMv9.4, a bunch of specific named additions to SME (shades of the Intel confusion around AVX512 ) are defined in ARMv9.5, and SME2p2 is defined in ARMv9.6.

Apple's M4 patches to LLVM/clang define it as ARMv8.7. I think I remember seeing claims there was something that's mandatory in ARMv9 that Apple hasn't implemented so they can't call it ARMv9 - maybe that's SVE but I'm 99% sure that SVE isn't strictly required in ARMv9. Now of course SME2 is not part of any ARMv8 iteration, but supporting MORE than the spec requires isn't really a problem I suppose.

Damn confusing. Guess my table is not comprehensive enough for all versions of SME

 

[mvprod123]

I thought M4 support SME only. Any other source mention that M4 supporting SME2 beside today announcement???

SME2 is part of ARMv9.4 and from the Wiki M4 uses ARMv9.2

Get Ready for Arm SME: Coming Soon to Android

Build next-gen mobile AI apps with SME2—no code changes needed. Accelerate performance across devices using top AI frameworks and runtimes.

community.arm.com

 

[Io Magnesso]

Get Ready for Arm SME: Coming Soon to Android

Build next-gen mobile AI apps with SME2—no code changes needed. Accelerate performance across devices using top AI frameworks and runtimes.

community.arm.com

View attachment 126994

Which is the ARM ISA version of Apple's 2024 CPU? Which one?
There is a possibility that ARM is simply arbitrarily grouped into SME2 but There is also the possibility of ordinary SME

 

[poke01]

Apples M4 core is v9.2A. It’s in their cpu optimisation guide

 

[DZero]

I am thinking... when ARM will start to use a small out of order core? In order ones is starting to struggle.

 

[mvprod123]

 

[Doug S]

Damn confusing. Guess my table is not comprehensive enough for all versions of SME

View attachment 126988

That table is wrong. ARM's own site clearly shows ARMv9.3 is where SME2 was defined:

https://developer.arm.com/documenta...scriptions/The-Armv9-3-architecture-extension

It also has links to all the ARMv8 and ARMv9 extensions to see what was added when.

EDIT: if you look at the ARMv9.2 tab at the very bottom it lists a bunch of optional features added in later releases of ARMv9.2. One of them is SME2p1 (i.e. the version of SME defined in ARMv9.4)

 

[Doug S]

Apples M4 core is v9.2A. It’s in their cpu optimisation guide

It was originally defined as ARMv8.7 in LLVM. I dug up the patch Apple submitted for that, it shows why:

+ // Technically apple-m4 is ARMv9.2a, but a quirk of LLVM defines v9.0 as
+ // requiring SVE, which is optional according to the Arm ARM and not
+ // supported by the core. ARMv8.7a is the next closest choice.

 

[Shivansps]

Rockchip unveils RK3668 10-core Arm Cortex-A730/Cortex-A530 SoC with 16 TOPS NPU, RK182X LLM/VLM co-processor - CNX Software

The Rockchip Developer Conference 2025 (RKDC!2025) is now taking place in Fuzhou, China, with some interesting announcements such as the Rockchip RK3668

www.cnx-software.com

NEw Rockchips SoC underway, the RK3688 and RK3668. With unannounced Cortex A730/A530 and also unnanounced ARM Magni GPU.