Apple A10 Fusion is ** Quad-core big.LITTLE **

[Nothingness]

Not sure many people have access to Linley Group, but they have an interesting article about Apple A10.

http://www.linleygroup.com/mpr/article.php?id=11697

 

[Arachnotronic]

Not sure many people have access to Linley Group, but they have an interesting article about Apple A10.

http://www.linleygroup.com/mpr/article.php?id=11697

Is this article worth buying? Like, is there real meat and potatoes here about the uArch that isn't yet in the public domain?

 

[Nothingness]

Is this article worth buying? Like, is there real meat and potatoes here about the uArch that isn't yet in the public domain?

Mostly no, except for one piece of die analysis that surprised me and that I need to get more thought into.

The article compares area against ARM-based competition, including perf/GHz and perf/area (though I disagree with their choice of averaging GBv3 and GBv4 which seems odd).

I don't think it's worth buying 🙂

 

[Arachnotronic]

Mostly no, except for one piece of die analysis that surprised me and that I need to get more thought into.

The article compares area against ARM-based competition, including perf/GHz and perf/area (though I disagree with their choice of averaging GBv3 and GBv4 which seems odd).

I don't think it's worth buying 🙂

Thanks, good to know that I can save the money 🙂

 

[witeken]

Can't wait for the A10X in the spring and the A11 next fall. A10X has already taped out and the A11's tape out is happening as we speak 🙂

I guess they need 10nm for a more impressive GPU improvement.

 

[name99]

https://en.wikipedia.org/wiki/AOMedia_Video_1

No hardware supports AV1 and will not likely until 2018 earliest, because AV1 hasn't been finalized yet, March 2017 is the target date.

Apple won't support open codecs though though since Apple has NOT INVENTED HERE(NIH) syndrome like many other big tech companies.

Oh for crying out loud. You do know that HEVC is an open spec, right? Just like h.264 before it, and MPEG4 before that, and AAC before that, all of which were/are Apple's primary codec.

 

[name99]

So.. Apple destroys any ST opponent even Intel, but is brutalized in MT by everyone (even Mediatek and AMD), except Qualcomm? Interesting...

This is simply not true. ("Apple is ... brutalized in MT by everyone".) Look at the numbers.

The reason appears to be that the ARM mobile SoCs do not provide enough memory performance to support 4, let alone 8 cores. The worst offenders utilize a single memory controller connected to a 64-bit wide bus and suffer from both bandwidth and latency (or if you prefer, queuing) problems. The more aggressive vendors try to improve things by using a 128-bit wide bus, which helps with bandwidth, but not with queuing.

You can invent toy benchmarks that run purely in cache, for which all 8 core of a standard high-end SoC can crank away without stamping over each other trying to reach RAM (although such a benchmark will, then, very soon force the SoC to throttle...), but for any real code memory is the real constraint.

This is not purely an "other ARM" problem, even Apple suffers from it. Going from one core to two, Apple's per core performance drops to about 80..85%, and with their one 3 core CPU so far, it dropped to only about 70%. There's a real engineering problem here in that, ideally you'd like more parallelism in your memory system (more RAM banks, more RAM pages, more controllers, deeper queues in the controllers) but all this stuff costs power and area, so it's not a great addition to a phone. Even so, Apple's trade-offs basically make sense ---they get a real performance boost from that second core --- whereas for ARM, especially in the supposed 4+4 mode, the extra cores are nonsense, pretty much guaranteed to spend a lot of time waiting on RAM because other cores submitted their requests first.

It's worth noting that, for example, XGene3, to try to deal with this problem, includes 8(!) memory controllers on the die to feed 32 cores. One controller per four cores, which may still be sub-optimal (ten might be better, though the more cores and controllers you have active, the better statistics average out to help you, so you aren't so hurt by the unfortunate moments when ALL your cores all want memory access at once).

 

[name99]

http://www.streamingmedia.com/Artic...rds-Based-Codec-and-Good-Riddance-111602.aspx



Even Apple can't stand the BS from the greedy patent pools.

That is the way to bet.
My guess is that Apple was planning to introduce 4K content along with h.265 as its standard 4K codec, and the patent pools demanded a change in terms. At which point Apple guessed that they could postpone h.265 pretty much as long as they liked and either the patent pools would break, or an acceptable alternative would come along.
Still not clear how this will play out. Presumably as alternatives to h.265 become more viable, the patent pools will crack and try to renegotiate. At which point does Apple go with them, or do they say "sayonara, guys, you had your chance and you blew it"?

 

[Andrei.]

The reason appears to be that the ARM mobile SoCs do not provide enough memory performance to support 4, let alone 8 cores. The worst offenders utilize a single memory controller connected to a 64-bit wide bus and suffer from both bandwidth and latency (or if you prefer, queuing) problems.

Such as?? Never ceased to be amazed by the claims you make.

Almost every single but the cheapest SoCs out there have dual memory controllers (2x32bit) and each memory controller has 2x16bit channels to the memory dies that seem to work independently. (If that's even correct and it's not 4x16 memory controllers from the get-go)

 

[cytg111]

Can't wait for the A10X in the spring and the A11 next fall. A10X has already taped out and the A11's tape out is happening as we speak 🙂

I guess A11 will show us if Apple can indeed walk on water or if its gonna be power reductions and feature sets like we've seen with Core over the last decade. Interresting times, looking forward to it.
If A11 jumps Core ST performance I am ready to jump ship 🙂.

 

[witeken]

I guess A11 will show us if Apple can indeed walk on water or if its gonna be power reductions and feature sets like we've seen with Core over the last decade. Interresting times, looking forward to it.
If A11 jumps Core ST performance I am ready to jump ship 🙂.

A10 still doesn't even have SMT and (high, 3GHz+) Turbo Boost yet. They won't improve ST performance much anymore, but there's still some very low-hanging fruit (no pun intended 😀) left.

 

[Nothingness]

I guess A11 will show us if Apple can indeed walk on water or if its gonna be power reductions and feature sets like we've seen with Core over the last decade. Interresting times, looking forward to it.

I'm curious too to see what A11 will bring 🙂

IPC improvements have already started slowing down it seems: ~10% for A10 over A9. OTOH they improved frequency a lot.

 

[Lodix]

A10 still doesn't even have SMT and (high, 3GHz+) Turbo Boost yet. They won't improve ST performance much anymore, but there's still some very low-hanging fruit (no pun intended 😀) left.

Unlike Intel, we see good improvements in the architecture of the ARM cpus each year. Not everything is frecuency for defining a good CPU (remember ~4W TDP for a phone ).

 

[witeken]

Unlike Intel, we see good improvements in the architecture of the ARM cpus each year.

Only because the architectural improvements are shifted by up to a decade or so. Which Intel architecture has similar IPC to Qualcomm Kryo? Exactly, some CPU long, long ago. The ARM vendors are just catching up, with Apple as the exception, 'cause their A10 has become ~on par. It won't be long until they also have to be satisfied with low improvements, at least in single thread, but in multithread Intel also has no problem at all with 28 core SKL E5 next year.

Don't forget that mobile has a ton more headroom because desktop is literally pushing the silicon to its limits. So your comparison with desktop is flawed. So, rather, just like the ARM vendors, we see good improvements in the architecture of the Intel Core m CPUs each year.

 

[name99]

Such as?? Never ceased to be amazed by the claims you make.

Almost every single but the cheapest SoCs out there have dual memory controllers (2x32bit) and each memory controller has 2x16bit channels to the memory dies that seem to work independently. (If that's even correct and it's not 4x16 memory controllers from the get-go)

So Andrei, what's YOUR explanation for
(a) Galaxy Note 7 (as an example) matching A10 in GeekBench Stream numbers (which suggests to me a single memory controller
(b) Galaxy Note 7 GB Multi results are only 2.3x the single core results (again, this is the pattern across high end devices, nothing specific to Samsung here).
?

 

[krumme]

So Andrei, what's YOUR explanation for
(a) Galaxy Note 7 (as an example) matching A10 in GeekBench Stream numbers (which suggests to me a single memory controller
(b) Galaxy Note 7 GB Multi results are only 2.3x the single core results (again, this is the pattern across high end devices, nothing specific to Samsung here).
?

I cant answer the question properly though i can guess some of it have to do with high st boost clock on the s7 and the given difficulties of using more cores. But why not ask apple?
This is a Apple big little thread.
But to me it seems loads of people still didnt get the memo.

Kudos to Andrei for showing the benefits of 4 core and even up to 8 cores in android chrome browsing a year back. A break of conventional wisdom and still is.

Kudos to Andrei for showing when big little started to get real benefits with the s6. State of the art reviewing imo.

So i am sure you can get a proper answer 🙂

 

[name99]

I cant answer the question properly though i can guess some of it have to do with high st boost clock on the s7 and the given difficulties of using more cores. But why not ask apple?
This is a Apple big little thread.
But to me it seems loads of people still didnt get the memo.

Kudos to Andrei for showing the benefits of 4 core and even up to 8 cores in android chrome browsing a year back. A break of conventional wisdom and still is.

Kudos to Andrei for showing when big little started to get real benefits with the s6. State of the art reviewing imo.

So i am sure you can get a proper answer 🙂

If you look at that article you will see a number of comments (including mine) that point out that what Andrei measured did not mean what he thought it meant. These technical points have never been responded to.
So, yeah, I'm not as convinced as you.

As for that S6 review that you like so much, let me quote from:
http://www.anandtech.com/show/9146/the-samsung-galaxy-s6-and-s6-edge-review/2
"The memory controller is new and supports LPDDR4 running at 1555MHz. This means that the Galaxy S6 has almost double the theoretical memory bandwidth when compared to.."

Note that SINGULAR there. Memory controller, not "memory controller(s)"...

 

[krumme]

I remember those comments. I dont have the technical insight to go into that discussion. But i dont have to. The market have shown Andrei was right.
Today we have barely nothing but big little except little quad a53.
You are in the middle of a apple big little thread.
Wake up and move on.

 

[name99]

I remember those comments. I dont have the technical insight to go into that discussion. But i dont have to. The market have shown Andrei was right.
Today we have barely nothing but big little except little quad a53.
You are in the middle of a apple big little thread.
Wake up and move on.

You would think that learning from the mistakes of the past is part of what will make Apple's solution substantially more performant than ARM's solution, no?
But I take it you're not interested in learning, just in waving the tribal flag?

 

[name99]

I, for example, am willing to learn from my mistakes. My first hypothesis, when Apple's hetero-core strategy became known, was that Apple would, at least in some way, for some purposes, allow all four cores to run simultaneously, the way you can run all eight cores of a big.LITTLE system. But once I ran the numbers on how poorly MP-scaling has worked across the entire ARM phone-core eco-system, I changed my mind.

It's still possible that Apple might have this in mind (or might have it in mind for the A10X, which will presumably have a 128b wide DRAM interface and twice the bandwidth of the A10) but I no longer consider it an obvious feature of the SoC --- for the reason's I've given, there's usually just not enough bandwidth available for it to be worth the attempt.

 

[krumme]

An a53 is in the order of 0.7mm2 incl L2 in the Samsung 20nm variant. Is it worth it to go to quad core vs dual core? Its hardly a budget killer. I think most will pay for it.

I dont think the average iphone user can tell the 5s from the 7 in regards to perf and probably most arm big cores could be ripped without most users noticing it.
So if little cores is used makes no difference. The big cores is plenty fast in a10. What matters is battery life. And big little is a solution to that.

 

[imported_ats]

I remember those comments. I dont have the technical insight to go into that discussion. But i dont have to. The market have shown Andrei was right.
Today we have barely nothing but big little except little quad a53.
You are in the middle of a apple big little thread.
Wake up and move on.

No we have a lot of marketing.

And A10 is not big.little, it is basically nothing like big little.

 

[witeken]

And A10 is not big.little, it is basically nothing like big little.

Source 🙂?

 

[coercitiv]

And A10 is not big.little, it is basically nothing like big little.

Can you give us more details on this please?

 

[Nothingness]

Can you give us more details on this please?

- big.LITTLE can work with all CPU's on; A10 can't
- big.LITTLE has separate L2 cache for each cluster; A10 seems to share half of L2 cache

IMHO that's all there is that matters. But I'm missing some coffee so I might have skipped something important 😀