Question Another potential big blow to Intel

[chrisjames61]

Microsoft going the Apple route and using their own ARM cpu's in Surface laptops and desktops and hardware for their data centers.

Intel falls on report Microsoft plans to design own chips for PCs and servers

Intel has famously had a long-running partnership with Microsoft as the primary processor maker for Windows PCs.

www.cnbc.com

 

[DrMrLordX]

So you are comparing 4 big cores + 4 small cores snapdragon 865 to 2 big cores + 4 small cores A13 in MT performance? And, even with half big cores A13 still achieves better performance and that's a proof that A77 is as good as Apple's cores?

In terms of perf/watt, how is A77 not better than A13 in MT scenarios? Or are you missing the point of what I am saying? We are talking about hypothetical WARM workloads here in a future MS Surface product. The likes of which the SQ1 currently struggles with in the Surface Pro X. Rest assured that the SQ1 is already working its butt off, and that its performance is indicative of its MT capabilities and its TDP limits. Assuming MS goes with an X1-based solution for Surface, you should expect more of the same, albeit with significantly better performance across the board. Likely a 4+4 arrangement aimed at M1, with worse performance but better power characteristics. It'll be competitive, but late to market, assuming MS actually makes good on their threats.

 

[naukkis]

In terms of perf/watt, how is A77 not better than A13 in MT scenarios? Or are you missing the point of what I am saying?

A13 has double the performance per core in those geekbench results. They are totally different league in there. Performance doesn't scale linearly, more like with third exponent. People still seem not to understand how good Apple cores are.

 

[Thala]

A13 has double the performance per core in those geekbench results. They are totally different league in there. Performance doesn't scale linearly, more like with third exponent. People still seem not to understand how good Apple cores are.

You still miss the point of what DrMrLordX was saying. He was talking about overall SoC performance/W and you are talking strictly about ST performance without any relation to power.

 

[naukkis]

You still miss the point of what DrMrLordX was saying. He was talking about overall SoC performance/W and you are talking strictly about ST performance without any relation to power.

Nope. There isn't any mention of ST-performance, only MT-performance. But A13 achieves those MT-performance figures with only half of big cores of S865. If we take third exponent as scaling reference that S865 with only half the big cores would consume 2^3/2 as much power as it does with 4 cores for that MT performance. So that S865 with same performance but only two big cores would consume something like 2^3*5W/2 ~ 20W of power.

Of course those numbers aren't exact as they are calculated from SOC power instead of core powers and there are also little cores - but it still is good reference as how efficient Apple cores are - at this time there simply isn't any other high-performance cpu cores that do come even close to that efficiency what Apple cores achieve.

Apple cores are so good that it's actually hard to understand.

EDIT: rethink calculations.

 

[Kenmitch]

Apple cores are

worthless if your not in the ECO system.

 

[naukkis]

worthless if your not in the ECO system.

Yes they are but why isn't Intel or AMD or somebody else doing as good cpu cores? Is the main reason that other big players shoot themselves at foot by using old not well suitable instruction set for high IPC-cores instead best available instruction set? End result is however that Apple could make cpu core that gives a phone as much single-thread power that x86 players can offer to no-power limits desktops - this situation isn't fine at all, other players should improve their approach or pretty soon only high-performance cpu design is sold together with Apple ecosystem.

.... Maybe it's nVidia which will bring other cpu designs on par again - but is nVidia ecosystem any better than Apple's?

 

[dacostafilipe]

Yes they are but why isn't Intel or AMD or somebody else doing as good cpu cores? Is the main reason that other big players shoot themselves at foot by using old not well suitable instruction set for high IPC-cores instead best available instruction set?

ARM does not simply make your CPU fast, it's not some kind of faire dust you can throw around and make everything fly.

Apple did not magically create a fast ARM Core, it invested a lot of resources to gradually improving its custom cores performance.

Stop using the instruction set to downplay the amount of work all those engineers did.

 

[naukkis]

Stop using the instruction set to downplay the amount of work all those engineers did.

I don't downplay any engineering, I just point out that where engineering ARM core they can for example just make their load-store engines bigger and more performing where x86 engineers are handicapped with legacy junk like total store order and instead of widening their design they just keep making complex hardware that masks cpu core to maintain that legacy compatibility like TSO. TSO means just that other cores see writes from other cores in program order thus not needing any other sync instructions - in poorly written and designed multithreaded code- which prevents cpu's store pipeline to rearrange cache-stores, like when there's 50 waiting stores to cache where needed cache lines are in L1 cache but one line is missing core can't do any stores before that missing line is loaded to cache. With weakly ordered memory model code execution can go on as long as there's free store buffer slots. And with TSO cpu core can't reuse store buffer slots which contains needed address's data if there is some other store between them - weakly ordered core could so needing less cache traffic and stalling core execution is more unlikely.

x86 designs want to operate their hardware just like weakly ordered cores do, but to do so they have to implement many tricks like locking cache lines with writes and release them in program order instead of normal cache behavior - that makes hardware more complex and specially debugging hardware design far more difficult - and that extra hardware maintaining those features just consumes power and die space that could be used to increase performance in designs that do not need those kind of tricks.

 

[Doug S]

I don't downplay any engineering, I just point out that where engineering ARM core they can for example just make their load-store engines bigger and more performing where x86 engineers are handicapped with legacy junk like total store order and instead of widening their design they just keep making complex hardware that masks cpu core to maintain that legacy compatibility like TSO. TSO means just that other cores see writes from other cores in program order thus not needing any other sync instructions - in poorly written and designed multithreaded code- which prevents cpu's store pipeline to rearrange cache-stores, like when there's 50 waiting stores to cache where needed cache lines are in L1 cache but one line is missing core can't do any stores before that missing line is loaded to cache. With weakly ordered memory model code execution can go on as long as there's free store buffer slots. And with TSO cpu core can't reuse store buffer slots which contains needed address's data if there is some other store between them - weakly ordered core could so needing less cache traffic and stalling core execution is more unlikely.

Since Apple's M1 supports a mode that enables TSO, I hope Andrei or some tries running the ARM build of Geekbench and SPEC and whatever else with TSO enabled and without to put this dumb argument to rest. There's a difference, but it is very small and making it out to be some massive advantage for ARM is ridiculous. If it was that big of a deal Intel would have introduced options for a more relaxed memory model long ago, or AMD would have made the switch when they introduced x86-64.

The main thing TSO does is make the hardware designers job a little harder, and the software writers job a little easier (read what Linus has to say about TSO versus memory models even more relaxed than ARM's relatively strong one, like Alpha's...suffice to say he's not a fan of relaxed memory models)

 

[moinmoin]

Yes they are but why isn't Intel or AMD or somebody else doing as good cpu cores?

As Intel has shown if no directly comparable competition is raising pressure the output remains at "good enough". It took AMD for Intel to finally raise the amount of cores. Now that AMD completely caught up and even passed Intel it could stagnate as well, but with Apple releasing M1 a bleeding edge ARM design finally enters the common laptop/desktop space, renewing competitive pressure. If that was an unexpected event for Intel and AMD (which it shouldn't, depending on the quality of their internal forecasting) we'll see the results of the ensuing R&D in 2-3 years at the earliest.