Review Andrei's Snapdragon 888 + Exynos 2100 review

[soresu]

But Qualcomm isn't using TSMC N5, at least Snapdragon 888 is also built using Samsung 5LPE process just like Exonys 2100.

Well that explains a lot about A14's increased power efficiency advantage this gen.

How depressing.

 

[soresu]

You're agreeing with my point. The first gen of every new "G" runs hot the first few years, and by the time that's under control some phone buyers start dreaming about (n+1)G.

2G was not even remotely new at that point which was practically at the time of 3G phones getting released, unless the hardware in my Nokia was just very old.

 

[AkulaMD]

It's an evolution of 7LPP. The next distinct (if that's what you want to call it) node step is 3GAE.

I thought that 4nm is supposed tu be a slightly improved version of 5nm instead of 7nm.

 

[JasonLD]

I thought that 4nm is supposed tu be a slightly improved version of 5nm instead of 7nm.

Well, It is still based on 7LPP.

 

[AkulaMD]

Well, It is still based on 7LPP.

View attachment 39713

From your diagram, if i read it correctly, the 4nm is indeed an improvement of the 5nm.

 

[Hitman928]

From your diagram, if i read it correctly, the 4nm is indeed an improvement of the 5nm.

And 5 nm is an improvement on 6 nm which is an improvement on 7 nm. The 'roots' of 4 nm are still with the 7 nm node, that was the question at hand. The 3GAE node will be very different than any of the previous nodes.

 

[Borealis7]

oops, n/m

 

[soresu]

And 5 nm is an improvement on 6 nm which is an improvement on 7 nm. The 'roots' of 4 nm are still with the 7 nm node, that was the question at hand. The 3GAE node will be very different than any of the previous nodes.

A question is will it be competitive with TSMC N3, let alone N3P?

Even with MBCFET I have my doubts.

Considering how behind Samsung seem to be on scaling it's not impossible that TSMC could still be quite competitive at the N3 nodes.

Hopefully though the major difference between MBCFET and finFET implementations will not drastically hamper efforts to spread oout capacity across available fabs for companies like AMD and nVidia.

 

[JasonLD]

A question is will it be competitive with TSMC N3, let alone N3P?

Even with MBCFET I have my doubts.

Considering how behind Samsung seem to be on scaling it's not impossible that TSMC could still be quite competitive at the N3 nodes.

Hopefully though the major difference between MBCFET and finFET implementations will not drastically hamper efforts to spread oout capacity across available fabs for companies like AMD and nVidia.

I don’t think the actual density difference between Samsung’s 3nm and TSMC 3nm will be that big on actual product. I recall A14 only had like 130mts/mm2(compared to theoretical 171mts/mm2 for N5) due to slowdown on SRAM scaling compared to logic.

 

[soresu]

I don’t think the actual density difference between Samsung’s 3nm and TSMC 3nm will be that big on actual product. I recall A14 only had like 130mts/mm2(compared to theoretical 171mts/mm2 for N5) due to slowdown on SRAM scaling compared to logic.

MBCFET has also has lower transistor density than finFET for a given pitch.

This offsets the power efficiency gains a bit.

 

[moinmoin]

A question is will it be competitive with TSMC N3, let alone N3P?

Andrei wrote in his review (the one this thread is about) that starting with 5LPE Samsung is finally matching TSMC's N7 in power efficiency, but still only at lower frequencies. TSMC's N5 is ahead. 3GAE likely will have to catch up with that first before taking on TSMC's N3.

 

[Doug S]

Andrei wrote in his review (the one this thread is about) that starting with 5LPE Samsung is finally matching TSMC's N7 in power efficiency, but still only at lower frequencies. TSMC's N5 is ahead. 3GAE likely will have to catch up with that first before taking on TSMC's N3.

Samsung is going to GAAFET for their 3nm, which is ahead of TSMC (who are sticking with FinFET for N3 and won't go GAA until 2nm in 2024) so they will get its reputedly significant power saving benefits early. That assumes they can get it working on schedule, switching to a new transistor type is not always easy.

While I'm sure Samsung would tell everyone is because they are ahead of TSMC's technology, it is quite possible that they weren't able to make FinFETs as power efficient as TSMC's (i.e. what Andrei measured) so they were forced to abandon ship on them a generation ahead of TSMC.

Some rumors have said Samsung would be able to ship GAAFET devices as early as this time next year, but I'm highly skeptical given that they were reported to have their first GAAFET prototype in late 2019. Getting something novel to work in the lab and getting it to work in mass production usually takes more than just two years. Also I would think that Intel would have talked to Samsung and seen where they were at and where their roadmap was going, and would have chosen them over TSMC if they were looking to take the lead.

 

[soresu]

Samsung is going to GAAFET for their 3nm, which is ahead of TSMC (who are sticking with FinFET for N3 and won't go GAA until 2nm in 2024) so they will get its reputedly significant power saving benefits early.

You seem to misunderstand that there exists not only a gap between Intel and everyone elses nodes in their naming schemes, but also a gap now between Samsung and TSMC's logic gate and metal pitch for a given named node.

Don't assume that just because Samsung call it 3nm that it corresponds to the pitches that TSMC will be working with on N3/N3P.

MBCFET does confer a power efficiency advantage over the finFET device at the same pitch yes - but it also loses transistor density too.

So designs that rely on more transistors per area, rather than more power efficient transistors could theoretically be at a disadvantage for an MBCFET process vs a finFET process on the exact same pitch.

That being said, as I mentioned in an earlier post based on what we already know of TSMC's superior finFET pitch scaling on current nodes, it is still highly likely that Samsung's 3GAE process could be on a larger pitch compared TSMC N3 to begin with, thus amplifying the MBCFET area disadvantage, and perhaps even eliminating some/all of the MBCFET power advantage over finFET.

 

[Doug S]

Power is more important than area in the smartphone world, so even if Samsung's process is less dense then if (and as I said that's a big IF) it is lower power it will be seen as superior.

People here pay WAY too much attention to density. Especially to the very useless "claimed density" figures which are never approached in real designs. Which then causes them to reach conclusions such as "N5 didn't scale as well as claimed" based on Apple die photos, without knowing whether Apple perhaps made decisions that reduced cache density as a consequence rather than TSMC falling short on its metrics.

Apple in particular does not care all that much about die size - the A14 is already smaller than many iPhone SoCs, so making a decision that increased the die size marginally but did something else they want (lower power, better performance, whatever) would not be unreasonable for them.

 

[moinmoin]

It's an interesting conundrum: In the end why everybody moves to "smaller" nodes is higher energy efficiency, this allows everybody to pack more performance in a given power envelope. But what sells customers onto smaller nodes even in face of rising costs for masks and validation is higher density, since that can counterbalances the rise in cost. If the cost is 40% higher but the area saving is 40% as well the move could be considered an economical no-brainer (of course the actual calculation is far more complex than this, with upfront and per wafer costs etc.). In addition to that density is actually the parameter that allows for further silicon level optimizations like adapting the silicon to high frequencies: The lower the density reachable the more room there is to loosen the density again. E.g. AMD's Zen 2/3 cores on N7 are not as area efficient as they could be, but that's by choice to reach the frequencies beyond what GloFo's 14/12nm was capable of.

 

[soresu]

without knowing whether Apple perhaps made decisions that reduced cache density as a consequence rather than TSMC falling short on its metrics.

Reduced density could well be a consequence of changing the design to suit higher frequencies without drastically increasing thermal hotspots for more CPU core dense SoC designs if the rumoured 12 core SoC is forthcoming.

 

[soresu]

People here pay WAY too much attention to density.

It all depends on what you are designing for.

Fab companies make a point of advertising their density figures - not for our sakes or that of the media, but rather for the silicon designers and their bean counters.

At the end of the day I'm sure that the various silicon architects/engineers would go crazy if they could without an area budget with only thought to yields and power, but at the end of the day area determines how many dies/SoC's their company can sell per wafer.

So it is by no means a less important metric at all for the companies actually designing the chips, and to some degree for us buying as it effects their pricing decisions too.

 

[Mopetar]

To some degree yields and power are a function of density. Packing transistors as densely as possible may lead to worse thermal performance or negatively affect yields. Eventually enough is learned about a process to understand how to maximize whatever characteristics (cost, performance, etc.) are the most important to whoever is building the chip. The density figures are usually just what's physically possible, not necessarily what's advisable or the best for all parts of the chip.

 

[Doug S]

Reduced density could well be a consequence of changing the design to suit higher frequencies without drastically increasing thermal hotspots for more CPU core dense SoC designs if the rumoured 12 core SoC is forthcoming.

If they are using the A14 core for the upcoming Mac SoC that might be the case, but I think there's a better than even chance they'll be using the A15 core. Apple seemingly pulling in the schedule for the A14 tapeout (I didn't see any rumors for A15...anyone?) along with TSMC rumored to have pulled in the mass production date for N5P and N3 earlier in Q2 of this and next year, respectively, would match up with that idea.

I don't want to go through the whole thing here in detail since its off topic, but it would make sense for Apple to want to start mass production of Mac AS wafers prior to iPhone SoC wafers going forward, to allow them to hit the back to school sales cycle which requires wide availability of new Mac models no later than August 1st. Fortunately they need far fewer wafers to serve Mac demand, which means they only need to ramp a month earlier - but they'd want to shoot for 2-3 months to give them more of a cushion since back to school is an even harder deadline than "new iPhone September release" which can and has been pushed back a bit more than once.

 

[soresu]

Apple seemingly pulling in the schedule for the A14 tapeout (I didn't see any rumors for A15...anyone?) along with TSMC rumored to have pulled in the mass production date for N5P

A14 is already in the market in the iPhone 12, and I'm pretty sure it is fabbed on the standard N5 node.

A15 is the generation projected to be on N5P:

Apple’s A15 Bionic will reportedly use Taiwan’s TSMC N5P node | Taiwan News | 2020/10/28

A15 chipset expected to go into mass production during third quarter of 2021

www.taiwannews.com.tw

 

[Doug S]

A14 is already in the market in the iPhone 12, and I'm pretty sure it is fabbed on the standard N5 node.

A15 is the generation projected to be on N5P:

Apple’s A15 Bionic will reportedly use Taiwan’s TSMC N5P node | Taiwan News | 2020/10/28

A15 chipset expected to go into mass production during third quarter of 2021

www.taiwannews.com.tw

Yes I know, I was talking about N5P being pulled in to make M2s in Q2 of this year using the A15 cores to hit the "back to school" schedule.

 

[bononos]

Indeed. The Snapdragon 888 and Exynos 2100 are on the same process using the same core alignment (X1, 3x A78, 4x A55). The Exynos even sports higher clockspeeds on most of their cores. It has less L2 cache than the Snapdragon 888 though. That Exynos 2100 throttles more tells an odd story.

Will Samsung move back to an inhouse design for their next gen?

 

[uzzi38]

Will Samsung move back to an inhouse design for their next gen?

For their CPU cores? Their core design team is already gone, so heavily doubt it.

 

[DrMrLordX]

Will Samsung move back to an inhouse design for their next gen?

Not likely, for reasons articulated by @uzzi38 . Once you let the talent go, it's hard to get it back.

 

[NTMBK]

Will Samsung move back to an inhouse design for their next gen?

Their in-house design was consistently worse than the Cortex alternative, while using more die area in the process. I'm pretty sure they're done with that.

However- we will apparently see an AMD GPU in their next flagship SoC!