MadRat
Lifer
- Oct 14, 1999
- 11,999
- 307
- 126
In your section about Prescott's little secrets it was no surprise that a more efficient L1 cache/L2 cache would have this effect. The cache weakness in the Northwood (compared to Prescott) is obviously overcome by the 800fsb. As clock speed increases then the front-side bus on the Northwood cannot cope with the L1 cache/L2 cache misses. The Prescott is less affected by the memory latency, due to fewer cache misses, therefore it is slightly more efficient only as clock speed increases. Its not like Prescott's L1 cache/L2 cache design is revolutionary or anything, so it shouldn't take too much of a higher clockspeed for the performance increase to flatten out to where the statistical difference again will be insignificant between the two.
This is a beef I have with the A64. The 128K L1 has been the baseline since the original K7 core. Its L1 design has now survived several process and architecture changes, and its obvious that the L1 is not efficient enough for the A64 - the larger L2 caches in A64 makes a noticeable difference in benchmarks that have even relatively small data sets. Nor is A64's L2 cache, with its 64-bit pathway, an improvement over old K7 technology. AMD should have moved to 192K or 256K L1, or even a trace cache, when they released the Opteron. The ClawHammer with 256K L1+256K L2 would have been probably a wiser lowend A64 design than the 128K L1+512K L2 design that was settled upon. I fully realize that AMD is nowhere near the size of Intel, but I'd of thought that AMD, with its modular philosophy in CPU design, could have pre-designed a larger or more efficient L1 cache by now. That, or of made the datapath to the L2 cache 128-bit or 256-bit DDR. Isn't the datapath to L2 cache more complicated in the long run?
This is a beef I have with the A64. The 128K L1 has been the baseline since the original K7 core. Its L1 design has now survived several process and architecture changes, and its obvious that the L1 is not efficient enough for the A64 - the larger L2 caches in A64 makes a noticeable difference in benchmarks that have even relatively small data sets. Nor is A64's L2 cache, with its 64-bit pathway, an improvement over old K7 technology. AMD should have moved to 192K or 256K L1, or even a trace cache, when they released the Opteron. The ClawHammer with 256K L1+256K L2 would have been probably a wiser lowend A64 design than the 128K L1+512K L2 design that was settled upon. I fully realize that AMD is nowhere near the size of Intel, but I'd of thought that AMD, with its modular philosophy in CPU design, could have pre-designed a larger or more efficient L1 cache by now. That, or of made the datapath to the L2 cache 128-bit or 256-bit DDR. Isn't the datapath to L2 cache more complicated in the long run?
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