anandtech Prescott review NOW UP! (anand inside)

[Ionizer86]

I'm no pro at architecture, but last I remember the 10 stage theoretical chip should go faster since along with the higher clock they can also pack ten pieces of data in there at once (assuming everything is linear and not branchy). I don't think the article touched upon multiple pieces of data in the pipeline at once.

 

[zephyrprime]

I don't think the article touched upon multiple pieces of data in the pipeline at once.

It almost seems like the author is under the mistaken impression that there's only one instruction flowing through the pipeline at once. His contentions would be valid if this were the case but this is never the case. The whole point of a pipeline is to pipeline; to have multiple ops in flight.

 

[Sohcan]

Originally posted by: zephyrprime

Now our 10 stage CPU can run at 2GHz, but at 2GHz we?ll have the exact same performance as the first CPU at 1GHz. Remember that although we?re running twice as fast, we have twice as many stages to make it through so the overall throughput is the same as the first 1GHz design.

Wait a second. I think this is wrong. The 10 stage pipeline cpu will have higher throughout. Can anyone clarify this?

being the intelligent CPU designers that we are, we would only extend the pipeline to 10 stages if we knew that we could make each clock period shorter than 0.5ns. And let?s say we do accomplish that, that we can get the clock period down to 0.33ns. Now design 2 can reach 3GHz, while design 1 can only reach 1GHz.

I think this is also wrong. Doesn't an increase in pipeline length by a factor N result in a less than factor N increase in clockspeed because there's a certain amount of additional circuitry needed to interface adjacent pipeline stages?

Yes, the explanation is very misleading. Their talk of "filling" a pipeline as having a first-order effect on performance implies that only one instruction is being dispatched down the pipe at a time, leading to half the clock-normalized throughput of a twice-as-long pipeline. But this completely ignores the fact that we're talking about a pipeline here...in the steady-state case (assuming a one instruction wide pipe), one instruction will be completed every cycle, regardless of whether the pipeline is 1 stage or 100 stages. So in the ideal case (which is, after all, what the article was trying to present), a 2 GHz 10-stage MPU will have twice the peak throughput of a 1 GHz 5-stage MPU. Of course, pipeline flushes from branch mispredictions and losses in the memory system due to the higher clockrate have a greater adverse effect on the longer pipeline...but between these relatively rare (but high impact) events, the two pipelines are going to be both finishing one instruction per cycle.

I also have to take exception to this comment:

Whatever their underlying motives for the move, Prescott?s design would have had to have been decided on at least 1 ? 2 years ago in order to be launched today.

Core feature freeze is more like a minimum of 3+ years before launch without affecting the release date.

 

[Anand Lal Shimpi]

Thanks for the heads up guys, we've been working on this nonstop and I didn't have a chance to go through and re-read all of my analogies

Take care,
Anand

 

[Anand Lal Shimpi]

Sohcan

I was trying to point a worst case scenario picture, if Intel were "panicked" into drastically redesigning a part of the P4 core. I was assuming 1 year for validation (which is the norm as far as I recall) and another year for the design changes themselves.

Take care,
Anand

 

[Sohcan]

Originally posted by: Anand Lal Shimpi
Sohcan

I was trying to point a worst case scenario picture, if Intel were "panicked" into drastically redesigning a part of the P4 core. I was assuming 1 year for validation (which is the norm as far as I recall) and another year for the design changes themselves.

Take care,
Anand

That's understandable...but there typically is 12-18 months of silicon debug before release and after first tapeout where there definitely are no changes going on without any sort of major impact to the schedule. The 12-18 months before tapeout, during which the physical layout is being done, also can't realistically have any significant changes to the core microarchitecture, especially something as major as increasing the pipeline depth by over 50%, which would likely have an impact on most of the core units. Realistically, I'd say 3 years is the minimum time after which the major core features can't be changed without an increasing impact on the original schedule.

It's just a minor nitpick, I enjoyed the article.

 

[MichaelD]

/reaches up
/touches the man

:Q

Oh....shiny....

I liked the article. As someone that has/had no knowledge about Prescott at all, it was informative for me. That said, I wouldn't buy one even if I had the money right now.

 

[Anand Lal Shimpi]

Sohcan

You're right, I should've stressed it as much longer than 1 - 2 years. My main goal was to make it very clear that the marketing folks at Intel didn't read AT a couple of months ago, see the Athlon 64 winning in some benchmarks, and then decide to add 11 new stages to Prescott's pipe.

MichaelD

Haha I'm glad you enjoyed the article (and the shinyness).

Take care,
Anand

 

[InlineFive]

I have to say I'm a bit dissapointed with Intel. Each processor release the new contendor is just as good as or worse then it's ancestor. Not to mention that basically their only tactic is to lengthen the pipeline to get more speed.

Boo Intel...

-Por

 

[jdogg707]

Originally posted by: PorBleemo
I have to say I'm a bit dissapointed with Intel. Each processor release the new contendor is just as good as or worse then it's ancestor. Not to mention that basically their only tactic is to lengthen the pipeline to get more speed.

Boo Intel...

-Por

Intel decided with the first P4's that clock speed was going to matter more than performance...it works when marketing because people still see more GHZ and think...wow....that's really fast. No one cares to actually investigate, so in reality, Intel isn't trying to full the people who know what they are talking about, because they aren't the ones spending the money on computers, they are marketing to those who don't have a clue or don't have the time to find out...even in an IT department, when you are explaining a budget, more GHZ for the same money seems a lot better, no matter if it really is or not.

BTW, Anand, great article, I like it when there is a good amount of technical information present, it makes for a great read.

 

[Ionizer86]

Originally posted by: PorBleemo
I have to say I'm a bit dissapointed with Intel. Each processor release the new contendor is just as good as or worse then it's ancestor. Not to mention that basically their only tactic is to lengthen the pipeline to get more speed.

Boo Intel...

-Por

Seems like it too. Many of their releases are not solid in terms of performance; it takes them another iteration or so to get the chip "right." AMD, on the other hand, delayed the K8 for a very long time, but I'd say the performance is solid upon release. We see the 2.0GHz A64 3200+ outperform the 2.2GHz AXP 3200+ on close to everything.

It also seems we've been slowing down in the last few years. CPU performance doesn't seem to be increasing as much as back in the pre-GHz days. The THG article (Yes, the one with the broken English) has a timeline, and it really seems like we're not getting that many releases recently. Maybe Intel could have released a Prescott 3.6 as a flagship to speed things up a bit in the CPU world

 

[InlineFive]

Originally posted by: Ionizer86

Originally posted by: PorBleemo
I have to say I'm a bit dissapointed with Intel. Each processor release the new contendor is just as good as or worse then it's ancestor. Not to mention that basically their only tactic is to lengthen the pipeline to get more speed.

Boo Intel...

-Por

Seems like it too. Many of their releases are not solid in terms of performance; it takes them another iteration or so to get the chip "right." AMD, on the other hand, delayed the K8 for a very long time, but I'd say the performance is solid upon release. We see the 2.0GHz A64 3200+ outperform the 2.2GHz AXP 3200+ on close to everything.

I would much rather have the release late and have it be a solid chip. Not to mention very competitive prices on the 3000+...

-Por

 

[Acanthus]

Originally posted by: PorBleemo

Originally posted by: Ionizer86

Originally posted by: PorBleemo
I have to say I'm a bit dissapointed with Intel. Each processor release the new contendor is just as good as or worse then it's ancestor. Not to mention that basically their only tactic is to lengthen the pipeline to get more speed.

Boo Intel...

-Por

Seems like it too. Many of their releases are not solid in terms of performance; it takes them another iteration or so to get the chip "right." AMD, on the other hand, delayed the K8 for a very long time, but I'd say the performance is solid upon release. We see the 2.0GHz A64 3200+ outperform the 2.2GHz AXP 3200+ on close to everything.

I would much rather have the release late and have it be a solid chip. Not to mention very competitive prices on the 3000+...

-Por

You dont think the 3.0ghz prescott will be competitively priced?

 

[bmg]

Originally posted by: andreasl
Anand failed to mention that this improvement in performance scaling is primarily from the increased L2 cache. In fact all other improvements in the core probably just turns up as noise in the scaling benchmarks compared with the bigger L2 cache. A Northwood with 1MB L2 would blow away Prescott completely. Just see what the P4EE does (although it has 2MB L3 instead)

I was going to post this very thing, but you beat me too it. The narrowing of the performance difference between Northwood and Prescott as the multiplier increases is clearly due to the effect of the larger L2 cache in Prescott becoming more noticable. There's most likely no other magic in Prescott that's involved. Think about the performance impact of increasing the processor core frequency (larger multiplier) while holding the bus frequency (and memory speed) constant. As an example, a 20% increase in processor core frequency won't give you a 20% processor performance improvement, due to the fixed bus frequency (200mhz in this case). As the cache size increases the performance dependence on the fixed bus and memory speed will be reduced, getting you closer to that ideal 20% (lower cache miss rate resulting in fewer accesses to memory).

 

[tedinde]

makes sense!!!

 

[us3rnotfound]

Remember what the end of the article said:

"To put it bluntly: Prescott becomes interesting after 3.6GHz; in other words, after it has completely left Northwood?s clock speeds behind."

I think Prescott has a lot more in store than what is presently evident.

 

[ViRGE]

Hey Anand, what's the power usage/output on the Prescott? Are the 100wt rumors are true?

 

[Acanthus]

Any chance of a follow up article on the Prescott?

I would like to see if the HT improvements were significant or not.

I would also like to see if SSE3 is a solid improvement on supporting applications. (edit: i know theres no SSE3 apps yet.)

 

[Anand Lal Shimpi]

ViRGE

Intel didn't provide reviewers with the thermal data on Prescott.

...but then again, there are lots of things that Intel doesn't provide us with that we still have access to

Pentium 4 3.20E - 89W
Pentium 4 3.40E - 103W
Pentium 4 3.60 - 103W

What's interesting is that the 3.60GHz Prescott seems to have the same thermals as the 3.40E. It looks like there may be a new stepping in the works that'll drop those figures a bit though, I'll see if I can do a bit more digging.

Take care,
Anand

 

[nick1985]

a64 > prescott

 

[Anand Lal Shimpi]

Acanthus

We did some preliminary HT tests on Prescott vs. Northwood, nothing too impressive. Remember that the majority of these improvements are designed to make up for the lengthened pipeline and won't really show their strengths until Prescott has done some clock scaling.

Ok I really need to pull myself away from the computer and go to bed

Take care,
Anand

 

[Tab]

Originally posted by: nick1985
a64 > prescott

word.

 

[nick1985]

Originally posted by: Anand Lal Shimpi
Acanthus

We did some preliminary HT tests on Prescott vs. Northwood, nothing too impressive. Remember that the majority of these improvements are designed to make up for the lengthened pipeline and won't really show their strengths until Prescott has done some clock scaling.

Ok I really need to pull myself away from the computer and go to bed

Take care,
Anand

only 565 posts anand? your not much of a dork are you :beer:

 

[Pariah]

Prescott doesn't seem to be much of a looker today, but I think the conclusion of most reviewers is that we are far from seeing the best Prescott has to offer. With a core that appears to scale better on a clock for clock basis than the Northwood, a design that will allow for very high clock rates, better multi-threaded application support in the future for the improved HT, SSE3 enhanced applications, DDR-II, PCI-Express, etc..., the Prescott will be quite a beast heading into 2005. It certainly looks a lot better than the P4 did at release compared to the PIII.

 

[Markfw]

Well, I hate to say it, but even the Intel fanatics even seem to be disappointed in Prescott. I hope Intel can scale before AMD runs away with the show. I don't want the tables too tipsy on AMD's side, or they will start to up their processor prices like Intel did 10 years ago. Competition is good for all of us !!