<< Sledge Hammer will have 4 HT IO Links to link with 3 other Hammer CPUs, and one link to go to the AGP Controller/South Bridge along with the DC DDR controller. >>
No. Sledgehammer will have 3 HT links. 2 for glueless SMP and 1 for IO. It supports up to 8 CPU configurations this way. I suck at ASCII so I'll refer you to the wealth of litterature links about the Hammer SMP to see how it's connected unless you're unsure of that.
<< This is someting I've been thinking about. First off, Anand mentioned that the HT Bus is a 8-bit bus (1 byte per clock cycle), and that seemed awful low, but then I looked at the diagrams from THG (see here) for both the Single Hammer CPU and the 4 way Hammer System, and each HT link was 6.4GB/ps!!!! The HT bus must be at least DDR, but then again, even a DDR 8-bit bus would need a 3.2GHz front side bus which can't be. So, I can't explain how AMD will get 6.4GB/ps of fsb bandwidth, but the bottom line is that Hammer will have it. >>
The HT links on Sledgehammer are 16-bit bi-directional running at 800MHz DDR. This gives it a maximum bandwidth of 3.2GB/s in both directions. Hence 6.4GB/s.