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AMD Zeppelin codename confirmed and perhaps 32 cores per socket

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mrmt said:
This. Plus Zeppelins are big and slow, exactly the traits you should expect of your brand new processor.
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Big and slow, perhaps... But airships are among the most efficient forms of air transportation ever created. Compared to the fuel economy of jets or helicopters.... much more economical. They may also be coming back for tourism purposes due to that efficiency.


The USS Los Angeles was quite successful for its time.
 
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Azuma Hazuki said:
I often wonder what the architecture would have been like with double the L2 cache with more associativity, speed, and lower latency. It looks to me like a hungry and chronically underfed animal.
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The L2 capacity likely would've been wasted by the slow bandwidth and only added to the power consumption and area. I think the actually ~ 2 wide int cores were quickly saturated. Then there were decoding throughput inefficiencies for 256b AVX code etc.

Also look how well Carrizo does (IPC wise) with half the L2 cache.


itsmydamnation said:
one thing that will be very interesting to see with Zen is what will the L1 latency be, i wouldn't be surprised to see 3 cycle but i expect 4.
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4 cycles according to the patch.


MiddleOfTheRoad said:
Big and slow, perhaps... But airships are among the most efficient forms of air transportation ever created. Compared to the fuel economy of jets or helicopters.... much more economical. They may also be coming back for tourism purposes due to that efficiency.
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Interesting point. If someone at AMD really thought along these lines, we'll likely never hear about it. Using that analogy above they didn't want to build a plane, which needs a lot of energy (leakage) just to create a lift force strong enough to overcome gravity. Instead they tried to avoid this energy toll as much as possible by using buoyancy (low leakage - smaller cores, low voltage) and a big airship (lots of the smaller cores) to efficiently carry a lot of payload (computational throughput at high perf/W). OK, I admit, this is made out of thin (or hot?) air. Just practicing my English skills. 😉

jhu said:
But Led Zeppelins are awesome.
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Not Le(a)d Zeppelins, but LED Zeppelins, looking a bit like this one? 😉
wdl_01.jpg

SCNR - and these are surely no LEDs.
 
Isnt the common association with zeppelins the Hindenburg. Hence why they are not called zeppelins anymore but airships.

Its an awful name for sure, couldn't have picked a worse one.
 
jhu said:
I was thinking of:
[Led Zeppelin image]
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They created the name based on an analogy of a lead balloon combined with the Hindenburg ship. My pun was intended. 😉


ShintaiDK said:
Isnt the common association with zeppelins the Hindenburg. Hence why they are not called zeppelins anymore but airships.

Its an awful name for sure, couldn't have picked a worse one.
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frozentundra123456 said:
All I can think of is the zeppelins flying around in Bioshock Infinite. Who knows what the product will be like, but it *is* a terrible name.
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C'mon, this is just a server MPU code name. No normal customer will pick such a "hot'n'burnin'" Zeppelin CPU from the shelves. 😉

BTW, was there such a discussion after Fudzilla leaked the Opteron MCM slide?
 
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ShintaiDK said:
Isnt the common association with zeppelins the Hindenburg. Hence why they are not called zeppelins anymore but airships.

Its an awful name for sure, couldn't have picked a worse one.
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You are clearly not a fan of classic rock music..... Considering the age of Jim Keller -- pretty sure that the name is likely an homage to Led Zeppelin as others have already pointed out.

Think about it -- arguably Led Zeppelin's best known song is Stairway To Heaven. Probably fits Jim Keller's personality judging from the video interviews I've seen of him. Think about it -- Robert Plant (who went solo after he was a member of Led Zeppelin) even had an album called "Now and Zen." Plant even recruited Led Zeppelin guitarist Jimmy Paige to play lead on that album..... Whoa, guys... Did I just inadvertently uncover the backstory about this codename for AMD?

If my hunch is actually true, then it is a truly epic name for a CPU.
 
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I thought the idea was that Zeppelins are effectively lighter than air while bulldozers/excavators are many tonnes.

But the Led Zeppelin theory makes more sense.
 
PPB said:
AMD could very well target good enough performance for the consumer and just keep this L3 cache shared between those 4 core blocks (making a smaller but faster L3 cache compared to BD) , and have HBM as a proper, big LLC in their server or HPC products.
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Just to clarify, in the post of mine that you quoted, I was referencing Zen version 1, the Zen that AMD is still saying will launch Q4 2016. I cannot imagine AMD attempting to put HPC on their first iteration of their Zen Opterons, for all of the reasons I stated in that post. It looks to me as if you are referencing referencing the Zen+ Opterons in the above quoted post, or the version that will come after the first generation.

If you were referring to the second generation of Zen Opterons, then I agree that it is quite likely that the second generation will use HBM. Also, I believe if AMD has plans on releasing APUs that do not use HBM, when they said they will be releasing them (2017), then unless they sell them dirt cheap, it is highly unlikely they will sell very many of them. I'm hoping that they use a minimum of 1GB HBM on their Zen APUs, with 2GB on their more expensive models, and I'm quite sure that is the reason AMD has said that the Zen APUs will be released ~6 months after the Zen Opteron.
 
JDG1980 said:
Cache latency was one of the big IPC killers on Bulldozer and its progeny. AMD's presentation slides specifically indicated improved cache performance for Zen, so at least there's an internal awareness of this issue and efforts taken to fix it.
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Someone speculated that the instruction cache that Sandy Bridge got is what helped it quite a bit versus Bulldozer. I wonder how Bulldozer/Piledriver would perform with one.

Also, lower latency caches (especially L1) limit overclocking, right?

AMD may have decided that, because they didn't have the money to make a desktop-oriented CPU design, that they would aim for clockspeed for marketing appeal. This approach seems to have reached its height with 9590.

Many post as if AMD had no idea what the weaknesses would be but I think strategic compromises were probably made. The problem with betting so much on clockspeed is that savvy buyers would notice that single core performance is critical (particularly for the years when games were barely making use of the core in an i5). AMD may have felt enterprise dollars were more important. Since Bulldozer didn't get very far in enterprise, the bet didn't pan out. I also assume the choice to make a design like Bulldozer was due to the financial squeeze (Intel tactics with OEMs, for instance) that had been put on the company years prior, the consequence of which was little R&D money. One report, citing an anonymous engineer from AMD (which may not be true), is that the company made very heavy reliance on automated tools as a cost-cutting measure, which also hampered the efficiency of the design. And, finally, it didn't help that the foundries AMD was using weren't making the progress they had intended to, in terms of a replacement for a 32nm high power node.
 
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swilli89 said:
Personal call outs not allowed


You are not allowed to act like a moderator
Markfw900
Anandtech moderator
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Yea, thats not gonna happen ... create a critical thread on, say surface pro3, get reported and you're shut down asap. different rules for different ppl with different agendas.. just how it is.


Mod callouts are not allowed.
Markfw900
 
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Glad I'm not the only one who's noticed the moderation is a bit...selective...around here ()🙂

Edit: And wow, the timing on that could not possibly have been any better. Please consider why mod callouts are occurring; there may be some useful information in the patterns.


Mod callouts are not allowed.
Boy, you really want to get in trouble, don't you.
Markfw900
 
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ShintaiDK said:
That slide screams fake. And its from back in august as the original one.
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So who did leak it and why? If something would leak that early, then probably out of talks with server guys.

Apart from those fake slides showing 6 ALU + 2x256b FMAC + 1 more FP pipeline, which were simply disproven by a GCC patch, it's now different in a way, that something on that slide, which was never heard before, has been confirmed as something real. What's your point?
 
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Huh, that one flew under my radar. Makes me think that all the noise about Zeppelin is a bit late, considering the fact that Fudzilla posted that all the way back in August.

But hey, at least we know they got the name right back then.
 
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