SarahKerrigan
Senior member
- Oct 12, 2014
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It was just SMT+CMP. The CMT comes from Chip MultiThreading reference.
T1 was non-SMT; it used fine-grained multithreading. T2/T3 was an oddity; i'd classify it somewhere between SMT and CMT. Significant logic (complete integer pipelines) were partitioned, two to a core, and each allocated to a group of four threads. As a result, two threads could issue per cycle, but it certainly wasn't a conventional SMT design.
Oracle no longer uses any related design, and hasn't since T4, which is a more conventional multithreaded OoO core.
Freescale, on the other hand, uses a very CMT-esque design in their e6500 core, although that's a very different target workload from anything AMD is targeting. An e6500 core has a pair of integer "virtual cores", with dedicated decode, issue, and execution logic, with a lot of similarity to the previous-generation e5500 core. Floating-point and VMX logic is shared.