An interesting reveal by a AMD representative though it remains yet to be officially confirmed. Zen supports a CMT + SMT design.
http://www.theregister.co.uk/2015/03/31/amd_opens_kimono_on_chip_futures_a_little_more/
http://www.pcper.com/news/General-Tech/Hints-things-come-AMD
"Consumer and commercial business lead Junji Hayashi told the PC Cluster Consortium workshop in Osaka that the 2016 release CPU cores (an ARMv8 and an AMD64) will get simultaneous multithreading support, to sit alongside the clustered multithreading of the company's Bulldozer processor families."
So I am guessing each module now consists of 2 big integer cores (IPC on par with Intel big cores like Haswell but I am guessing they are aiming higher as Skylake is the real competition) . 4 ALU and 3/4 AGU. Each integer core supports SMT to better utilize the resources of that big integer core for multithreaded workloads. The integer cores themselves will be basically a wider and much more powerful version of the Jaguar core. Low latency instruction execution, high IPC and power efficient cores. The Zen module itself follows a CMT design with instruction fetch and L2 caches being shared. My guess is a 2 MB shared L2 cache per module. The L3 will be shared across all modules.
This 4 thread Zen module with 2 MB L2 cache should be quite small at 16FF+ or 14LPP. I am guessing roughly 20 sq mm (accounting for the significantly larger integer cores and the wider 256 bit FPU) given that Steamroller was 29.47 sq mm on 28nm.
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6926864&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F4%2F4359912%2F06926864.pdf%3Farnumber%3D6926864
The question is does Zen use High density libraries like Carrizo. I doubt the server and high end desktop versions are using HDL and my guess is High performance libraries to enable 4 Ghz clock speeds. There might be a 2 module Zen APU (8 threads) for 15w which uses HDL for better efficiency at lower clocks. But for desktop and server I see Zen being used with high performance libraries.
When Jim Keller said they are looking to take the best of Jaguar and Bulldozer I think this was what he meant. CMT in itself is a good idea but Bulldozer was a flawed implementation. The Bulldozer integer core needed to be a wide and big machine with massive IPC. I am confident Keller has rectified that mistake. SMT is very useful when you have a big integer core. Zen looks to take the best of AMD's big and small core architectures and turn it into something very competitive.
I am thinking AMD will have more details at their Financial Analyst Day on May 6th 2015.
http://phx.corporate-ir.net/phoenix.zhtml?c=74093&p=irol-analystday
For a Q2 or Q3 2016 Zen/K12 release AMD should be taping out the chips in Q2 2015. The next 12 - 15 months are going to be very interesting.
I expect a few people to come in to this thread and keep talking about AMD's shrinking R&D budget and their imminent demise and how AMD Zen has no chance to compete with Intel Skylake. But I am sure AMD will prove the doubters wrong. :thumbsup:
http://www.theregister.co.uk/2015/03/31/amd_opens_kimono_on_chip_futures_a_little_more/
http://www.pcper.com/news/General-Tech/Hints-things-come-AMD
"Consumer and commercial business lead Junji Hayashi told the PC Cluster Consortium workshop in Osaka that the 2016 release CPU cores (an ARMv8 and an AMD64) will get simultaneous multithreading support, to sit alongside the clustered multithreading of the company's Bulldozer processor families."
So I am guessing each module now consists of 2 big integer cores (IPC on par with Intel big cores like Haswell but I am guessing they are aiming higher as Skylake is the real competition) . 4 ALU and 3/4 AGU. Each integer core supports SMT to better utilize the resources of that big integer core for multithreaded workloads. The integer cores themselves will be basically a wider and much more powerful version of the Jaguar core. Low latency instruction execution, high IPC and power efficient cores. The Zen module itself follows a CMT design with instruction fetch and L2 caches being shared. My guess is a 2 MB shared L2 cache per module. The L3 will be shared across all modules.
This 4 thread Zen module with 2 MB L2 cache should be quite small at 16FF+ or 14LPP. I am guessing roughly 20 sq mm (accounting for the significantly larger integer cores and the wider 256 bit FPU) given that Steamroller was 29.47 sq mm on 28nm.
http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6926864&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F4%2F4359912%2F06926864.pdf%3Farnumber%3D6926864
The question is does Zen use High density libraries like Carrizo. I doubt the server and high end desktop versions are using HDL and my guess is High performance libraries to enable 4 Ghz clock speeds. There might be a 2 module Zen APU (8 threads) for 15w which uses HDL for better efficiency at lower clocks. But for desktop and server I see Zen being used with high performance libraries.
When Jim Keller said they are looking to take the best of Jaguar and Bulldozer I think this was what he meant. CMT in itself is a good idea but Bulldozer was a flawed implementation. The Bulldozer integer core needed to be a wide and big machine with massive IPC. I am confident Keller has rectified that mistake. SMT is very useful when you have a big integer core. Zen looks to take the best of AMD's big and small core architectures and turn it into something very competitive.
I am thinking AMD will have more details at their Financial Analyst Day on May 6th 2015.
http://phx.corporate-ir.net/phoenix.zhtml?c=74093&p=irol-analystday
For a Q2 or Q3 2016 Zen/K12 release AMD should be taping out the chips in Q2 2015. The next 12 - 15 months are going to be very interesting.
I expect a few people to come in to this thread and keep talking about AMD's shrinking R&D budget and their imminent demise and how AMD Zen has no chance to compete with Intel Skylake. But I am sure AMD will prove the doubters wrong. :thumbsup:
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