AMD talks Barcelona

[Viditor]

Originally posted by: Acanthus

Im not seeing the argument either, its not like AMD is showing off working Barcelona samples either.

Well, let's hit the "Wayback Machine" and compare today to a year ago...

1. Starting in August 2005, Intel began dropping hints and some specs about C2D.
2. In Feb 06, Intel claimed that Conroe would outperform equivalent AMD chips by 20% (note that this was ~5 months prior to launch)
3. In March, Intel showed the first Conroe at IDF (but didn't allow it out to reviewers for independent benches)
4. In May/June, Reviewers got their hands on them and in July it was launched.

Today...
1. Starting in June 06, AMD began dropping hints and some specs on Barcelona
2. This month, AMD claims that it will perform 40% better than Cloverton (note that this is ~5 months before launch)
3. First showing? (maybe IDF as well?)


The timelines are pretty damn close...

 

[hardwareking]

but at the same clock speed it might be safe to assume that penryn will consume less power than a core 2 duo or core 2 quad chip.

 

[Viditor]

Originally posted by: IntelUser2000

4. Penryn IS a dumb shrink in that if you run a Penryn chip and a Conroe chip side by side at the same clockspeed, the only time you'd go faster on Penryn is if the software has been written with SSE4 code...and that won't be happening anytime soon. (it certainly doesn't effect todays programs)

No. It's almost a dumb shrink.

1. It'll have Hyperthreading
2. It'll have 50% more cache
3. Intel hints about additional architectural improvements

Pentium III/4's had straight shrinks, only adding more cache. Dothan wasn't a straight shrink either. Anand had an overview about it.

Fair enough (and props to DMLX as well)...
I don't want to get into another argument with Duvie about what the cache will do for performance (it pisses him off, and there's nothing worse than a pissed off Duvie!)
However for most consumer applications (and I don't think he'll disagree with this), an increased cache isn't a huge thing...though you are right and I stand corrected in that it WILL be a performnce change.

As to the HT, I am very dubious about it effecting performance at all on a multicore CPU...certainly not to a very great degree.

 

[Viditor]

Originally posted by: hardwareking
but at the same clock speed it might be safe to assume that penryn will consume less power than a core 2 duo or core 2 quad chip.

No, Penryn should consume MUCH less power core for core at the same clock...unless the added "bits" change that.
High-k Metal gates are a very big deal...

 

[ahock]

If Penryn consumes much less power then we can say that this will hit higher clock rate at same 65W power of conroe.

 

[Nemesis 1]

Originally posted by: Viditor

Originally posted by: Nemesis 1

Your own words. Since K8l isn't in production yet. We won't see them until at least 6 months after they start product or does AMD have better manufactoring abilities than Intel. Intels demo of penryn shows it working in programms . AMD demo showed it working in task manager . Only . So Amd more than likely has to do 1 or 2 more respins of the core before it can go into production . After they get an exceptable core than 6 months from that date we well see processors going out to DELL and other oems.

What makes you think Barcelona isn't in production yet?
My guess is that AMD will demo it across the street from the Spring IDF...why should they do it sooner?

This is a bad week for ya . your not doing well.

Your guess about amd demoing out side of spring IDF can't happen.

Why is that you may ask?

Because Intel canceled this years spring IDF.

 

[Nemesis 1]

Originally posted by: Viditor

Originally posted by: Nemesis 1

I'm with Furen on this...
I'm not sure what the Mitosis project has to do with Penryn or derivatives.
Mitosis isn't even close to being implemented (if it ever is). It is an interesting concept that is based mainly on a new type of compiler.

If you do a search through the forums, we had some really good discussions about Mitosis when the rumours about "reverse hyperthreading" first came out...

Of course you would stand with Furen on this . But why would intel introduce H/T into a mult core processor . When most programms are single threaded??
Unless Intels new H/T is able to use more cores to run 1 thread. Thats hyper threading also. We all know intel bought the Russian company Elbrus in 04. Now if you read this link . You will see that penryns Compiler is much improved with some pretty cool things it can do. Also read anand's report on penrtn Intel has 23% room with the number of transitors it uses , What do you think intel is doing with those transitors.

You said penryn was a dumb shrink. Many times. But what we know now its way more than that.

http://techreport.com/etc/2006q4/fall-idf/index.x?pg=1

Heres a quote from above link.


The bulk of SSE4's 50 or so instructions is comprised of new compiler vectorization primitives, which should make it easier for compilers to translate software written in high-level languages into effectively parallelized code and data structures. These new instructions encompass both integer and floating-point operations, and include provisions for dual- and quad-word multiplication, blending, and format conversions. SSE4 also has some related "media accelerator" functions that expand SSE's capabilities. Among them are four instructions that round floating-point values to integers and a floating-point dot product capability that should prove especially useful for graphics. Taken together, Intel expects these new instructions to help further the traditional promise of SSE as an accelerator for multimedia, 3D gaming, graphics, and scientific computing.

To be perfectly fair tho. I didn't exspect to see H/T until. Nehalem. I really believe thats still the case but if intel brings it with Penryn thats cool.

I don't think you understand Mitosis...or compilers.
1. Chips don't have compilers...compilers are software
2. 90% of getting Mitosis to work has nothing to do with the chips, it involves changing the software industry. The hardware just allows it to happen...
3. HT has nothing to do with speculative threading (Mitosis). (not sure why you think it does...)
4. Penryn IS a dumb shrink in that if you run a Penryn chip and a Conroe chip side by side at the same clockspeed, the only time you'd go faster on Penryn is if the software has been written with SSE4 code...and that won't be happening anytime soon. (it certainly doesn't effect todays programs)[/quote]

Well its pretty sure thing that you don't understand compilers or mitosis. You should have read the link to it I gave you. Than you would understand the SSE4 importance to mitosis.

As for compilers It would seem I know a bit more than . Your point 1)
The registers inside the core are managed by the software compiler which is also in the core.
Your point 2. Penryn has a much improved compiler and new ssse4 instructions which are required to make mitosis work..
Your point 3 AMD was talking about reverse H/T . H/T has everthing to do with mitosis. Its just the new intel version won't use 1 processor to read 2 threads . It will use 2 or more cores to work on 1 thread . with a multi core cpu you don't need to use H/T to split the core to read more threads . You need the available cores to work on 1 or 2 threads at the same time. Again if you would have read the mitosis link you would know this.
Your point 4 requires no reply from me as your only baiting and spreading fud.

The bulk of SSE4's 50 or so instructions is comprised of new compiler vectorization primitives, which should make it easier for compilers to translate software written in high-level languages into effectively parallelized code and data structures. These new instructions encompass both integer and floating-point operations, and include provisions for dual- and quad-word multiplication, blending, and format conversions. SSE4 also has some related "media accelerator" functions that expand SSE's capabilities. Among them are four instructions that round floating-point values to integers and a floating-point dot product capability that should prove especially useful for graphics. Taken together, Intel expects these new instructions to help further the traditional promise of SSE as an accelerator for multimedia, 3D gaming, graphics, and scientific computing.

To be perfectly fair tho. I didn't exspect to see H/T until. Nehalem. I really believe thats still the case but if intel brings it with Penryn thats cool.

 

[BrownTown]

person who knows what they are talking about: Viditor

person who doesn't: Nemesis 1

that is all.

 

[Viditor]

Originally posted by: Nemesis 1

Well its pretty sure thing that you don't understand compilers or mitosis. You should have read the link to it I gave you. Than you would understand the SSE4 importance to mitosis.

I have read the link before, actually...
How about one from Intel on what Mitosis actually is and what it does...
Intel's Mitosis White Paper

First, the reason for the program...

any time a compiler has to parallelize two pieces of code, it has to consider all potential dependences. It has to analyze whether one piece of code might write something in a given memory location that another piece of code may read. Unfortunately, in most cases, a compiler doing this only has an approximate view of the memory locations that are being touched by every single instruction. As a result, whenever the compiler has to detect potential dependences, it tends to be over-conservative. If the compiler cannot prove that two instructions are independent, it presumes they are dependent. This means when the compiler generates the code, it assumes a huge number of dependences that don't exist or very rarely exist. The code ends up overly serialized and misses many opportunities for parallelization

In other words, current compilers must be conservative with dependencies...now the Mitosis solution.

Speculative threads could revolutionize how we parallelize applications. Compilers would no longer have to be conservative. Instead, they could be optimistic. Instead of generating code for the worst case, compilers could generate for the common case. The result would be a much higher degree of parallelism and a significant gain in performance

A brilliant idea, but how do we make it work?
First the software (compiler):

Mitosis relies on both hardware and software (compiler) support to work. On the software side, the Mitosis compiler is responsible for analyzing the program, and locating the sections of it that can efficiently be executed in parallel. A key component of this analysis is the identification of sections of code whose corresponding precomputation slices have a very low computation overhead. Other conventional aspects such as workload balance also need to be considered

Intel has one of the best software teams around, but this project is MASSIVE (certainly more difficult than the design of C2D)! It must also be distributed, tested, and utilized by the software community...not exactly a 1-2 year project (just ask the EPIC guys).

What about the hardware?

On the hardware side, Mitosis is built on top of a multi-core and/or multithreaded processor. The main extension required is support for buffering and multiversioning in the memory hierarchy. Buffering is needed to keep the speculative state until the thread is verified and can be committed. Multiversioning is required to allow each variable to have a different value for each of the threads that are running in parallel. This is needed because every thread is executing a piece of code that started out with sequential semantics, but now, parallelized in threads, is being worked on simultaneously with values that were previously supplied in different points in time in the program

As you can see Intel is certainly headed in that direction, but the buffering and multiversioning isn't part of Penryn (at least not part of what we've seen, and that would be a HUGE change!), and certainly HT has nothing to do with it (though it does sound similar).

Now let's address your confusion about what SSE does...
SSE stands for Streaming SIMD Extensions.
You can think of SSE as a type of macro register that allows for simultaneous calculations to be performed from a call made in the software. This frees up the general register integer and FP work needed to be done by a significant amount.

The first SSE added 8 registers and 70 new instructions.

SSE2 and SSE3 added another 144 instructions which were predominantly geared towards media encoding

For SSE4, I think you saw the words "compiler vectorization primitives" and "parallelized code" without really reading the rest...
Firstly, remember that Nehalem is to be a CSI based processer...
Second, remember that one of the original goals of CSI was to create a single platform for both Xeon and Itanium (which operates in EPIC only)...
Now read this line again...
"The bulk of SSE4's 50 or so instructions is comprised of new compiler vectorization primitives, which should make it easier for compilers to translate software written in high-level languages into effectively parallelized code and data structures"

As to why they are introducing it in Penryn, it seems to me to be the same scenario they followed with Prescott...where they introduced the hardware for EM64T but didn't activate it. SSE4 needs to be in the marketplace and be used by codewriters before it becomes effective.

 

[Regs]

Mitosis will take a lot of work. Just like waiting for programmers to make use of quad core. If you're not into video encoding they're practically useless.

It almost seems like one of AMD's idea. Bank on it, wait until the idea is obsolete, but enjoy the free press while they can.

 

[hardwareking]

OFF TOPIC:
I wonder what title will be given to the review of Barcelona?
How does revenge of the sith sound?Or how about return of the Jedi?

Anyway it'll be cool if they used one of those cause Intel Core was The Empire Strikes Back.

 

[Nemesis 1]

Well I guess well just wait and see. Well probably see Penryn before K8L.

AMD dec.15 anaylist day meeting showed AMD'S true charicter. Lieing to the public about the state of the company with only 15 days l;eft in the quarter. Thousands of investors lost millions of dollars based off the meeeting. AMD can not be trusted to tell the trueth . and have lost all credability.

 

[BrownTown]

Originally posted by: Nemesis 1
Well I guess well just wait and see. Well probably see Penryn before K8L.

Why even post if you have no clue whats going on?

 

[SickBeast]

Originally posted by: hardwareking
OFF TOPIC:
I wonder what title will be given to the review of Barcelona?
How does revenge of the sith sound?Or how about return of the Jedi?

Anyway it'll be cool if they used one of those cause Intel Core was The Empire Strikes Back.

Attack of the Clones.

 

[BrownTown]

No, see that should be the prequel like in real life when AMD used to just copy Intel's parts instead of making their own. Barcelona would certainlly make sense to be "Retrun of the Jedi", if it really does retake the crown. IF not than it can just be the end of "Empire Strikes Back" like where Luke/AMD thinks they are safe in cloudland, but really Intel/Darth is waiting right around the corner to caputure them / release Penryn

 

[IntelUser2000]

No, Penryn should consume MUCH less power core for core at the same clock...unless the added "bits" change that.
High-k Metal gates are a very big deal...

Some versions will, some won't.

http://www.vr-zone.com/?i=4140

Wolfdale: 3.5-4.0GHz @ 57W

But then:
http://www.hkepc.com/bbs/itnews.php?tid=723070&starttime=0&endtime=0

"The 45nm Core 2 Duo, codenamed Wolfdale, is releasing in the end of this year, however, though it should be more power save, Intel decided to keep its TDP also at 65W. Such decision is made between a balance of performance and market value. It is stating that 65W TDP is already low enough for mainstream market, a lower TDP couldn?t give more significant effect to the market."

"Starting from G Stepping, all Quad Core except Extreme edition would set at 95W TDP including the existing Kentsfield and upcoming 45nm Yorkfield."


One reason is the vastly increased clock speeds. Increasing the clock speeds beyond 20% brought by 65nm process will require voltages. 15% more voltage and 15% more frequency will mean no power consumption decrease. Probably a bit on the lower clock speeds, but its safe to say most of the high performance mainstream won't vary a lot from the current ones.

 

[Viditor]

Originally posted by: IntelUser2000

No, Penryn should consume MUCH less power core for core at the same clock...unless the added "bits" change that.
High-k Metal gates are a very big deal...

Some versions will, some won't.

http://www.vr-zone.com/?i=4140

Wolfdale: 3.5-4.0GHz @ 57W

But then:
http://www.hkepc.com/bbs/itnews.php?tid=723070&starttime=0&endtime=0

"The 45nm Core 2 Duo, codenamed Wolfdale, is releasing in the end of this year, however, though it should be more power save, Intel decided to keep its TDP also at 65W. Such decision is made between a balance of performance and market value. It is stating that 65W TDP is already low enough for mainstream market, a lower TDP couldn?t give more significant effect to the market."

"Starting from G Stepping, all Quad Core except Extreme edition would set at 95W TDP including the existing Kentsfield and upcoming 45nm Yorkfield."


One reason is the vastly increased clock speeds. Increasing the clock speeds beyond 20% brought by 65nm process will require voltages. 15% more voltage and 15% more frequency will mean no power consumption decrease. Probably a bit on the lower clock speeds, but its safe to say most of the high performance mainstream won't vary a lot from the current ones.

I've seen that VR-zone article so many times...IMHO it's just BS (no dis to you IU2).
Their only source is themselves...in other words this is their guesstimate. It reminds me of the HKEPC article that said AMD wasn't going to have a quad core until mid-2008...

Note that it also says that Yorkfield and Wolfdale will be available in Q3 07, which we know for a fact isn't true...

 

[coldpower27]

Originally posted by: Viditor

Originally posted by: IntelUser2000

No, Penryn should consume MUCH less power core for core at the same clock...unless the added "bits" change that.
High-k Metal gates are a very big deal...

Some versions will, some won't.

http://www.vr-zone.com/?i=4140

Wolfdale: 3.5-4.0GHz @ 57W

But then:
http://www.hkepc.com/bbs/itnews.php?tid=723070&starttime=0&endtime=0

"The 45nm Core 2 Duo, codenamed Wolfdale, is releasing in the end of this year, however, though it should be more power save, Intel decided to keep its TDP also at 65W. Such decision is made between a balance of performance and market value. It is stating that 65W TDP is already low enough for mainstream market, a lower TDP couldn?t give more significant effect to the market."

"Starting from G Stepping, all Quad Core except Extreme edition would set at 95W TDP including the existing Kentsfield and upcoming 45nm Yorkfield."


One reason is the vastly increased clock speeds. Increasing the clock speeds beyond 20% brought by 65nm process will require voltages. 15% more voltage and 15% more frequency will mean no power consumption decrease. Probably a bit on the lower clock speeds, but its safe to say most of the high performance mainstream won't vary a lot from the current ones.

I've seen that VR-zone article so many times...IMHO it's just BS (no dis to you IU2).
Their only source is themselves...in other words this is their guesstimate. It reminds me of the HKEPC article that said AMD wasn't going to have a quad core until mid-2008...

Note that it also says that Yorkfield and Wolfdale will be available in Q3 07, which we know for a fact isn't true...

Not entirely accurate, the cache sizes on it are most likely correct. However considering it's timestamp and the information we have now, some information on there is simply out of date.

Like some of the new information that has come to light.

Yorkfield is likely due as a Core 2 Extreme in Q4 2007 this year, with the mainstream varaints and Wolfdale derivatives in the 1st Quarter 2008. Likely to be January. Similar to the Presler and Cedar Mill variants of Late 2005/Early 2006.

There is also the rumors of half step multipliers now for Penryn derivatives, so that will be interesting allowing 166MHZ intervals on FSB 1.33GHZ parts.

Yorkfield is looking to be a MCM like Kentsfield but instead of 2 Conroe's it uses to Wolfdale's.

The rest of an educated guess, since Intel likes to release 2P server grades of Core Architecture at around the same time as the desktop equivalents, Harpertown should also be due around the same time as Yorkfield and Wolfdale are.

On another note, Hyper Threading for the moment I am skeptical if it will exist on Penryn derivatives, that is something we will have to see.

 

[IntelUser2000]

I've seen that VR-zone article so many times...IMHO it's just BS (no dis to you IU2).
Their only source is themselves...in other words this is their guesstimate. It reminds me of the HKEPC article that said AMD wasn't going to have a quad core until mid-2008...

Note that it also says that Yorkfield and Wolfdale will be available in Q3 07, which we know for a fact isn't true...

Timelines can always change, but specs are usually more accurate. Take a look at the Intel TDP roadmap for HKEPC. Wolfdale is rated at 65W, and Yorkfield is 95W, which will be similar as the G stepping Kentsfield. The XE versions are in the same category as the XE Kentsfield.

 

[Keysplayr]

Originally posted by: coldpower27

Originally posted by: Viditor

Originally posted by: IntelUser2000

No, Penryn should consume MUCH less power core for core at the same clock...unless the added "bits" change that.
High-k Metal gates are a very big deal...

Some versions will, some won't.

http://www.vr-zone.com/?i=4140

Wolfdale: 3.5-4.0GHz @ 57W

But then:
http://www.hkepc.com/bbs/itnews.php?tid=723070&starttime=0&endtime=0

"The 45nm Core 2 Duo, codenamed Wolfdale, is releasing in the end of this year, however, though it should be more power save, Intel decided to keep its TDP also at 65W. Such decision is made between a balance of performance and market value. It is stating that 65W TDP is already low enough for mainstream market, a lower TDP couldn?t give more significant effect to the market."

"Starting from G Stepping, all Quad Core except Extreme edition would set at 95W TDP including the existing Kentsfield and upcoming 45nm Yorkfield."


One reason is the vastly increased clock speeds. Increasing the clock speeds beyond 20% brought by 65nm process will require voltages. 15% more voltage and 15% more frequency will mean no power consumption decrease. Probably a bit on the lower clock speeds, but its safe to say most of the high performance mainstream won't vary a lot from the current ones.

I've seen that VR-zone article so many times...IMHO it's just BS (no dis to you IU2).
Their only source is themselves...in other words this is their guesstimate. It reminds me of the HKEPC article that said AMD wasn't going to have a quad core until mid-2008...

Note that it also says that Yorkfield and Wolfdale will be available in Q3 07, which we know for a fact isn't true...

Not entirely accurate, the cache sizes on it are most likely correct. However considering it's timestamp and the information we have now, some information on there is simply out of date.

Like some of the new information that has come to light.

Yorkfield is likely due as a Core 2 Extreme in Q4 2007 this year, with the mainstream varaints and Wolfdale derivatives in the 1st Quarter 2008. Likely to be January. Similar to the Presler and Cedar Mill variants of Late 2005/Early 2006.

There is also the rumors of half step multipliers now for Penryn derivatives, so that will be interesting allowing 166MHZ intervals on FSB 1.33GHZ parts.

Yorkfield is looking to be a MCM like Kentsfield but instead of 2 Conroe's it uses to Wolfdale's.

The rest of an educated guess, since Intel likes to release 2P server grades of Core Architecture at around the same time as the desktop equivalents, Harpertown should also be due around the same time as Yorkfield and Wolfdale are.

On another note, Hyper Threading for the moment I am skeptical if it will exist on Penryn derivatives, that is something we will have to see.

Well, there are an extra 99 million core logic transistors (is that 49.5million per core in a dual core chip? Or 24.75 million for a quad core chip?) in Penryn than Conroe, excluding any L2 caches. Hyperthreading is a better than average possibility here. Not that Core 2 actually needs HT, but it couldn't hurt? (famous last words). hehe.

I hope Barcelona comes out swinging hard. Just to keep Intel on it's toes.

 

[Viditor]

Originally posted by: coldpower27
I've seen that VR-zone article so many times...IMHO it's just BS (no dis to you IU2).
Their only source is themselves...in other words this is their guesstimate. It reminds me of the HKEPC article that said AMD wasn't going to have a quad core until mid-2008...

Note that it also says that Yorkfield and Wolfdale will be available in Q3 07, which we know for a fact isn't true...

Not entirely accurate, the cache sizes on it are most likely correct. However considering it's timestamp and the information we have now, some information on there is simply out of date.

Like some of the new information that has come to light.

Yorkfield is likely due as a Core 2 Extreme in Q4 2007 this year, with the mainstream varaints and Wolfdale derivatives in the 1st Quarter 2008. Likely to be January. Similar to the Presler and Cedar Mill variants of Late 2005/Early 2006.

There is also the rumors of half step multipliers now for Penryn derivatives, so that will be interesting allowing 166MHZ intervals on FSB 1.33GHZ parts.

Yorkfield is looking to be a MCM like Kentsfield but instead of 2 Conroe's it uses to Wolfdale's.

The rest of an educated guess, since Intel likes to release 2P server grades of Core Architecture at around the same time as the desktop equivalents, Harpertown should also be due around the same time as Yorkfield and Wolfdale are.

On another note, Hyper Threading for the moment I am skeptical if it will exist on Penryn derivatives, that is something we will have to see.[/quote]

I accept your estimates as quite possible CP...I find no error in your assumptions.
The thing that sticks in my craw is that the VR-zone piece is posted as "news", and the format is that of a leaked roadmap. For instance, the "3.5-4.0GHz" is a pure WAG (and not a very likely one...)!
I have no problem with estimates or logical opinions, but to post an article like that without labeling it as such is just shoddy...
/rant

On another note, I agree with you on Hyperthreading...it really doesn't make sense to implement it on Penryn (though putting the circuits in place might).

 

[Hard Ball]

Originally posted by: IntelUser2000

They are not talking about SSE performance.

Are they?? I bet they are talking about Linpack. Why??:

1. They are talking about Barcelona and Clovertown, its obviously server chips
2. One of the most respected floating point benchmarks is Linpack
3. Linpack talks are always about the theoretical ability(Conroe can do 4 FLOPS/cycle, its dual core, so it can do 8 FLOPS/cycle in theory, but not in measured synthetic benchmarks, and nowhere in reality)
4. Conroe has 2x Linpack performance over Netburst in theory, and that came from SSE enhancements.

Barcelona = 3.6 x Dual Core Opteron

3.6/2 cores = 1.8

2x improvement per clock in Linpack, but slightly lower clock speeds make it 1.8x.

Not really, it's not the norm for AMD (or most semicons) to refer to SIMD instructions as executed by the "floating point engiene", usually reserved for x87. Remeber, Barcelona does 4 double precision FP ops per cycle per core (FADD + FMUL); x87 shares ports with SIMD units.

 

[coldpower27]

Originally posted by: keysplayr2003

Originally posted by: coldpower27

Originally posted by: Viditor

Originally posted by: IntelUser2000

No, Penryn should consume MUCH less power core for core at the same clock...unless the added "bits" change that.
High-k Metal gates are a very big deal...

Some versions will, some won't.

http://www.vr-zone.com/?i=4140

Wolfdale: 3.5-4.0GHz @ 57W

But then:
http://www.hkepc.com/bbs/itnews.php?tid=723070&starttime=0&endtime=0

"The 45nm Core 2 Duo, codenamed Wolfdale, is releasing in the end of this year, however, though it should be more power save, Intel decided to keep its TDP also at 65W. Such decision is made between a balance of performance and market value. It is stating that 65W TDP is already low enough for mainstream market, a lower TDP couldn?t give more significant effect to the market."

"Starting from G Stepping, all Quad Core except Extreme edition would set at 95W TDP including the existing Kentsfield and upcoming 45nm Yorkfield."


One reason is the vastly increased clock speeds. Increasing the clock speeds beyond 20% brought by 65nm process will require voltages. 15% more voltage and 15% more frequency will mean no power consumption decrease. Probably a bit on the lower clock speeds, but its safe to say most of the high performance mainstream won't vary a lot from the current ones.

I've seen that VR-zone article so many times...IMHO it's just BS (no dis to you IU2).
Their only source is themselves...in other words this is their guesstimate. It reminds me of the HKEPC article that said AMD wasn't going to have a quad core until mid-2008...

Note that it also says that Yorkfield and Wolfdale will be available in Q3 07, which we know for a fact isn't true...

Not entirely accurate, the cache sizes on it are most likely correct. However considering it's timestamp and the information we have now, some information on there is simply out of date.

Like some of the new information that has come to light.

Yorkfield is likely due as a Core 2 Extreme in Q4 2007 this year, with the mainstream varaints and Wolfdale derivatives in the 1st Quarter 2008. Likely to be January. Similar to the Presler and Cedar Mill variants of Late 2005/Early 2006.

There is also the rumors of half step multipliers now for Penryn derivatives, so that will be interesting allowing 166MHZ intervals on FSB 1.33GHZ parts.

Yorkfield is looking to be a MCM like Kentsfield but instead of 2 Conroe's it uses to Wolfdale's.

The rest of an educated guess, since Intel likes to release 2P server grades of Core Architecture at around the same time as the desktop equivalents, Harpertown should also be due around the same time as Yorkfield and Wolfdale are.

On another note, Hyper Threading for the moment I am skeptical if it will exist on Penryn derivatives, that is something we will have to see.

Well, there are an extra 99 million core logic transistors (is that 49.5million per core in a dual core chip? Or 24.75 million for a quad core chip?) in Penryn than Conroe, excluding any L2 caches. Hyperthreading is a better than average possibility here. Not that Core 2 actually needs HT, but it couldn't hurt? (famous last words). hehe.

I hope Barcelona comes out swinging hard. Just to keep Intel on it's toes.

There are an extra few transistors but using Anandtech given data they claim 23 million transistors more per core over the existing 49.5 mil per core we have now. So an increase of 47% in core logic per core, SSE4 is in that budget, so HyperThreading I agree is a possibility, though I currently doubt it at this point in time.

I agree, I actually hope Barcelona is a sucessful product for AMD's sake. I am hoping for good pricing for Intel Core 2 Duo's this year. We need AMD's K8L/K10 to be successful for that to continue to be the case.

 

[coldpower27]

Originally posted by: Viditor

Originally posted by: coldpower27

Originally posted by: Viditor
I've seen that VR-zone article so many times...IMHO it's just BS (no dis to you IU2).
Their only source is themselves...in other words this is their guesstimate. It reminds me of the HKEPC article that said AMD wasn't going to have a quad core until mid-2008...

Note that it also says that Yorkfield and Wolfdale will be available in Q3 07, which we know for a fact isn't true...

Not entirely accurate, the cache sizes on it are most likely correct. However considering it's timestamp and the information we have now, some information on there is simply out of date.

Like some of the new information that has come to light.

Yorkfield is likely due as a Core 2 Extreme in Q4 2007 this year, with the mainstream varaints and Wolfdale derivatives in the 1st Quarter 2008. Likely to be January. Similar to the Presler and Cedar Mill variants of Late 2005/Early 2006.

There is also the rumors of half step multipliers now for Penryn derivatives, so that will be interesting allowing 166MHZ intervals on FSB 1.33GHZ parts.

Yorkfield is looking to be a MCM like Kentsfield but instead of 2 Conroe's it uses to Wolfdale's.

The rest of an educated guess, since Intel likes to release 2P server grades of Core Architecture at around the same time as the desktop equivalents, Harpertown should also be due around the same time as Yorkfield and Wolfdale are.

On another note, Hyper Threading for the moment I am skeptical if it will exist on Penryn derivatives, that is something we will have to see.

I accept your estimates as quite possible CP...I find no error in your assumptions.
The thing that sticks in my craw is that the VR-zone piece is posted as "news", and the format is that of a leaked roadmap. For instance, the "3.5-4.0GHz" is a pure WAG (and not a very likely one...)!
I have no problem with estimates or logical opinions, but to post an article like that without labeling it as such is just shoddy...
/rant

On another note, I agree with you on Hyperthreading...it really doesn't make sense to implement it on Penryn (though putting the circuits in place might).

The clock rates are hard to say if they are accurate, they also have numbers for Altair, so it's hard to say at this point if either set will come to pass.

Though considering that Intel did show off Presler early in the game at 2.0GHZ, and the final shipping silicon reached 3.73GHZ in the Extreme variant. With Intel showing off Dual Core variants at 2.13GHZ now, the upper 3.5GHZ+ clock rates seem like a possibility

A reasonable estimate remains at Low to Mid 3.x GHZ for Quad's and Mid to High 3 GHZ for Duals and the 4GHZ versions for Duals coming in only if AMD's Antares Dual Core has a high enough performance level, though likely at higher then 65W TDP. Though I don't expect this to come to pass as Intel is pushing Quad Core now to put larger pressure on AMD's production capacity with their Native design which is a large single die.

 

[CTho9305]

Originally posted by: SickBeast
I'm thinking that if intel finally stops being stubborn and integrates a memory controller into the C2D chips, they will absolutely dominate AMD performance wise. Why have they resisted doing this for so long?

A friend of mine @ intel said they gave it to a new team at a design center in India and they totally screwed up the project.

Originally posted by: Viditor

Originally posted by: Duvie
I am sooo tired of rehashing the cache argument again...i wont....However I can tell you I know an app that is obviously loading large chunks into the L2 cache. the L2 cache runs at the clock speed thus is tremendously faster then using the memory. However it is clear from my testing it uses blocks larger then 1mb cache and can use chunks larger then 2mb of cache....I have tested this fromm 4mb down to 1mb and the gains are huge...the AMD goes from performing 2x slower to 5x slower in some of these test.

I think as the cache gets larger there is more opportunity for apps to load things into it. At 512kb I think it is file size limited. Why your argument may be correct in terms of Intel compensation, I think my argument is also correct. I think only some can take advanatge of it. however since Intel shares its cache in pools it offers the ability of some of these huge cache cpus they have coming of really taking advantage of the speed of the L2 cache....It runs at clock speed...for me that is SRAM running at 3.2ghz....

Fair enough Duvie...
To clarify though, would it be fair to say that:

1. The large cache is only more effective with apps that fall within those specific ranges (i.e. in this case between 1-4MB) and that they quickly become much slower when you use chunks that exceed the 4MB level
2. The vast majority of apps do not fall into this category
(can you think of any besides F@H?)

one thing that needs to happen is AMD needs to add a 4th execution unit as Intel did

I haven't found an app/OS combo yet that actually retires 4 ops/clock...of course that could just be my lack of experience. Have you observed this happening, and on which software?

Cheers

You don't need to retire 4 ops per cycle consistently. You get benefit if there is ever a situation where N ops are ready to execute and you only have N-1 units available to execute them. That's why it's not a linear performance gain though - very few programs can sustain high IPCs.

Mitosis will take a lot of work. Just like waiting for programmers to make use of quad core. If you're not into video encoding they're practically useless.

It almost seems like one of AMD's idea. Bank on it, wait until the idea is obsolete, but enjoy the free press while they can.

It's from academia, and it's not super-new - look at the dates on some of those publications. See also this paper from 1995.