AMD talks Barcelona

[nyker96]

this defintely sound too good to be true, every techie site who looked at Barcelona chip design said it's barely gonna be a match for intel quads at Q3/2007. The talk of 40% is probably in niche cases. But of course, I do wish it is true. That will surely help to drive down quad prices like crazy and usher in a new era of quad chips.

from a quick browse of other comments here it seems we all pretty much just guessing here except that 'hard ball' fella who seems to know the inside track. But in any case, the 65nm process AMD showed so far is definitely less than encouraging. I do hope they work out the kinks in their 65nm or in one article I've read IBM is selling a new 65nm process that claims to push AMD X2 core to 3.5. Buy that technology isn't a bad idea. Just put bacelona on a decent process at release time.

 

[Duvie]

Originally posted by: Furen

Originally posted by: Dadofamunky
I think AMD is nuts not to beef up their L2s/L3s. Intel is already smokin' them and even talking about, what, 8MB shared L2 between four cores? I can't see how this wouldn't provide some performance benefit across the board. If AMD sticks with the effective 512KL2/512KL3 per core I can't see how they can break out of 2nd place. That type of scheme just makes no sense to me. Why are they having so much trouble with larger caches? (Or ANY caches right now.) My uninformed speculation is that the enhanced execution cycles in K10 would be offset by longer waits due to the limited space in the caches. Still, we'll see.

Intel is also on a roll. Talking about a 1.8x delta vs. Clovertowns is basically meaningless. Let's see some new A64X4 chips with a full 1 MB L3 cache per core on a 65nm process, 3.0 GHz clock speeds, upgraded next-gen IMCs with DDR3, a serious fix for their cache latency problems, and unlocked multipliers. That's the only thing that would possibly keep me from getting a C2D or C4D by the end of this year. But I think Intel's pretty much invincible right now.

Increasing the size of the cache is the easiest way to increase performance (aside from ramping up clocks). AMD doesn't do it because the die-size increases too much for the little performance gain. Yes, cache helps out in games and the like but aside from games there's not much of a benefit to having a bigger cache.

K8L will support DDR3, the motherboards with DDR3 support won't come 'till next year, though. Not that it matters since DDR3 is just higher-latency DDR2 with more bandwidth.

K8L will double the data width for L2 (as far as I know) from 128bits to 256bits. This should be a HUGE thing.

I have yet to hear anything official on just how AMD will increase the IPC for this architecture though I've heard of out-of-order stores, increasing the CPU width, improving x86 decoder efficiency, increasing buffers, increasing prefetcher efficiency, increasing all kinds of internal data buses, etc. AMD only says "improved IPC cores" which just about any combination of the things I mentioned above could accomplish.

It is quite obvious by my Folding at Home evidence and the prowess of C2D's in superpi that Intel can take advantage of their L2 cache in several computational programs as well...Not just games....

 

[StopSign]

Originally posted by: Dadofamunky
That's the only thing that would possibly keep me from getting a C2D or C4D by the end of this year. But I think Intel's pretty much invincible right now.

You mean C2Q?

 

[SunnyD]

Originally posted by: Duvie

I would also liek to see INtel incorporate HTT type technology as well....

Isn't that what Intel's CSI is supposed to be?

 

[aka1nas]

Originally posted by: SunnyD

Originally posted by: Duvie

I would also liek to see INtel incorporate HTT type technology as well....

Isn't that what Intel's CSI is supposed to be?

I thought Nehalem would be the first chip with CSI support.

 

[bobsmith1492]

Originally posted by: Furen

Originally posted by: Dadofamunky
I think AMD is nuts not to beef up their L2s/L3s. Intel is already smokin' them and even talking about, what, 8MB shared L2 between four cores? I can't see how this wouldn't provide some performance benefit across the board. If AMD sticks with the effective 512KL2/512KL3 per core I can't see how they can break out of 2nd place. That type of scheme just makes no sense to me. Why are they having so much trouble with larger caches? (Or ANY caches right now.) My uninformed speculation is that the enhanced execution cycles in K10 would be offset by longer waits due to the limited space in the caches. Still, we'll see.

Intel is also on a roll. Talking about a 1.8x delta vs. Clovertowns is basically meaningless. Let's see some new A64X4 chips with a full 1 MB L3 cache per core on a 65nm process, 3.0 GHz clock speeds, upgraded next-gen IMCs with DDR3, a serious fix for their cache latency problems, and unlocked multipliers. That's the only thing that would possibly keep me from getting a C2D or C4D by the end of this year. But I think Intel's pretty much invincible right now.

Increasing the size of the cache is the easiest way to increase performance (aside from ramping up clocks). AMD doesn't do it because the die-size increases too much for the little performance gain. Yes, cache helps out in games and the like but aside from games there's not much of a benefit to having a bigger cache.

K8L will support DDR3, the motherboards with DDR3 support won't come 'till next year, though. Not that it matters since DDR3 is just higher-latency DDR2 with more bandwidth.

K8L will double the data width for L2 (as far as I know) from 128bits to 256bits. This should be a HUGE thing.

I have yet to hear anything official on just how AMD will increase the IPC for this architecture though I've heard of out-of-order stores, increasing the CPU width, improving x86 decoder efficiency, increasing buffers, increasing prefetcher efficiency, increasing all kinds of internal data buses, etc. AMD only says "improved IPC cores" which just about any combination of the things I mentioned above could accomplish.

Intel has the advantage because they are always 1-2 die shrinks ahead; they can afford extra die space for more cache since the die is smaller to start with.

Oh, also AMD chips need extra room for the memory controller; I don't know how significant it is sizewise.

 

[coldpower27]

Originally posted by: bobsmith1492

Originally posted by: Furen

Originally posted by: Dadofamunky
I think AMD is nuts not to beef up their L2s/L3s. Intel is already smokin' them and even talking about, what, 8MB shared L2 between four cores? I can't see how this wouldn't provide some performance benefit across the board. If AMD sticks with the effective 512KL2/512KL3 per core I can't see how they can break out of 2nd place. That type of scheme just makes no sense to me. Why are they having so much trouble with larger caches? (Or ANY caches right now.) My uninformed speculation is that the enhanced execution cycles in K10 would be offset by longer waits due to the limited space in the caches. Still, we'll see.

Intel is also on a roll. Talking about a 1.8x delta vs. Clovertowns is basically meaningless. Let's see some new A64X4 chips with a full 1 MB L3 cache per core on a 65nm process, 3.0 GHz clock speeds, upgraded next-gen IMCs with DDR3, a serious fix for their cache latency problems, and unlocked multipliers. That's the only thing that would possibly keep me from getting a C2D or C4D by the end of this year. But I think Intel's pretty much invincible right now.

Increasing the size of the cache is the easiest way to increase performance (aside from ramping up clocks). AMD doesn't do it because the die-size increases too much for the little performance gain. Yes, cache helps out in games and the like but aside from games there's not much of a benefit to having a bigger cache.

K8L will support DDR3, the motherboards with DDR3 support won't come 'till next year, though. Not that it matters since DDR3 is just higher-latency DDR2 with more bandwidth.

K8L will double the data width for L2 (as far as I know) from 128bits to 256bits. This should be a HUGE thing.

I have yet to hear anything official on just how AMD will increase the IPC for this architecture though I've heard of out-of-order stores, increasing the CPU width, improving x86 decoder efficiency, increasing buffers, increasing prefetcher efficiency, increasing all kinds of internal data buses, etc. AMD only says "improved IPC cores" which just about any combination of the things I mentioned above could accomplish.

Intel has the advantage because they are always 1-2 die shrinks ahead; they can afford extra die space for more cache since the die is smaller to start with.

Oh, also AMD chips need extra room for the memory controller; I don't know how significant it is sizewise.

At most Intel is 1 optical node ahead, but there is also the factor of Intel's cache on a given process is of superior density to AMD's on the same node. So Intel can throw generous amounts of cache on it's cores not only because of the node advantage but also their cache expertise.

Core logic is typically the lower density transistor stuff on a die, the DDR2 K8's added quite a bit to the die space, that is a factor to some degree.

 

[Regs]

Die shrinks are one thing, though lithography is another. In that case who's to say is better? I'm sure Intel is experienced from trying to keep the prescott cool

 

[imported_Questar]

Originally posted by: A554SS1N
Any reason why AMD would miss out K9 from the architecture naming? I.e. all this talk abut K10 being the name doesn't make sense?

The K9 project was killed in the summer of 2003 - Google it to find the exact date.

Remember, this chip is not K10, it's a spin of K8.

 

[Fox5]

Originally posted by: Nemesis 1
Not really when you factor in the lower clockspeeds. Its only 1.8 faster at same clock.

I doubt we will see K8L at 2.5 ghz for quit some time after its first release.

Got a link where AMD says its K10

But is this comparing quad core to quad core (which amd does not currently have) or quad core to amd's old dual core.

 

[SickBeast]

To be honest, I'm still running an Athlon XP at 2200mhz. Modern CPUs feel like overkill, and I have yet to see a truly creative use of modern CPUs that makes them worthwhile, gaming aside. Why do people need quad cores and insane CPU speeds aside from gaming and maybe rendering?

If you guys can find a good reason for me to upgrade I'll save up for barcelona. Otherwise I'm gonna ride this chip out until it burns up!

 

[Aluvus]

Originally posted by: A554SS1N
Any reason why AMD would miss out K9 from the architecture naming? I.e. all this talk abut K10 being the name doesn't make sense?

http://www.imdb.com/title/tt0097637/

 

[Regs]

Originally posted by: Questar

Originally posted by: A554SS1N
Any reason why AMD would miss out K9 from the architecture naming? I.e. all this talk abut K10 being the name doesn't make sense?

The K9 project was killed in the summer of 2003 - Google it to find the exact date.

Remember, this chip is not K10, it's a spin of K8.

Says who? The die has been drastically altered. The cache hierarchy has been changed. It works on a different socket. It will be the first native quad core design. As for IPC advancements, only AMD knows. Though what I said so far should draw the line clear enough that this is no spin off the K8.

Actually I think AMD is dropping the k# labelling all together. Barcelona is the name they gave it.

 

[IntelUser2000]

.

Because to be honest AMD has stated this all ready 10 times over. We don't know what 40% means. It all marketing mombo jumbo. And if you want to talk big words with college mates go ahead.

Want to know???

http://www.behardware.com/news/8484/amd-to-demonstrate-the-quad-core.html

"About performances, AMD announces respectively 13% and 46% improvements with TCP OLTP and SPECfp compared to a Xeon 5355"

I assume they meant to say TPC not TCP.

 

[RaynorWolfcastle]

Originally posted by: SickBeast
To be honest, I'm still running an Athlon XP at 2200mhz. Modern CPUs feel like overkill, and I have yet to see a truly creative use of modern CPUs that makes them worthwhile, gaming aside. Why do people need quad cores and insane CPU speeds aside from gaming and maybe rendering?

If you guys can find a good reason for me to upgrade I'll save up for barcelona. Otherwise I'm gonna ride this chip out until it burns up!

Honestly nice DVD decoding/upsampling requires quite a bit of horsepower; as does playback of HD-DVD and Blu-Ray. I know that my Opteron 165 @ 2.5 GHz can't smoothly upconvert DVDs to 1920x1080 with the post-processing filters I'd like to run on the video.

As for the AMD announcement, I'm intrigued but it'll stay in the "I'll reserve judgment until I see benchies" camp for now.

 

[BrownTown]

The problem of course is that even if they take the crown they will have to weather a new wave of processors in the 3-6 months after that. Not saying that AMD won't take the crown, but for starters quad cores are not a very high volume part by any means, and Intel will likely go up a speed bin to 2.93G for their quad cores if deemed nescecarry. And then you have the 45nm 12MB cache quad cores which are being said to have HyperThreading (I know, I don't beleive it either, but all the roadmaps say it), so you might see a 3.2G 12MB cache part comming out verse a 2.5G 6MB cache part, and AMD really better hope its IMC and improved IPC are worth ALOT because its gonna be giving up all kinds of clockspeed and cahce advantages to Intel.

 

[GEORGIAGRIT]

Hi
Y'all mind a little question from a newbie thats looking to build an AM2 machine?
Seems to me AMD has a bit more savy when desigining and anticipating future favorite bells and whistles (such as Athlon XP maybe). I've noticed a few articles popping up about Physics cards for some of those lesser used slots. Anyone know if possibly AMD might have a design advantage on making use of those in the future? Seems thats the next huge leap in gaming.
Great thread BTW, I hope Ive put this thought in the right one.

 

[SickBeast]

Originally posted by: Regs

Originally posted by: Questar

Originally posted by: A554SS1N
Any reason why AMD would miss out K9 from the architecture naming? I.e. all this talk abut K10 being the name doesn't make sense?

The K9 project was killed in the summer of 2003 - Google it to find the exact date.

Remember, this chip is not K10, it's a spin of K8.

Says who? The die has been drastically altered. The cache hierarchy has been changed. It works on a different socket. It will be the first native quad core design. As for IPC advancements, only AMD knows. Though what I said so far should draw the line clear enough that this is no spin off the K8.

Actually I think AMD is dropping the k# labelling all together. Barcelona is the name they gave it.

I agree with Regs.

I actually just read that Barcelona has been re-designed from the ground up and is 80% "different" from the K8.

Will the Barcelona run on AM2?

 

[imported_Questar]

Originally posted by: Regs

Originally posted by: Questar

Originally posted by: A554SS1N
Any reason why AMD would miss out K9 from the architecture naming? I.e. all this talk abut K10 being the name doesn't make sense?

The K9 project was killed in the summer of 2003 - Google it to find the exact date.

Remember, this chip is not K10, it's a spin of K8.

Says who? The die has been drastically altered. The cache hierarchy has been changed. It works on a different socket. It will be the first native quad core design. As for IPC advancements, only AMD knows. Though what I said so far should draw the line clear enough that this is no spin off the K8.

Actually I think AMD is dropping the k# labelling all together. Barcelona is the name they gave it.

Says Who?

AMD. Phil Hester to be exact.

 

[Viditor]

Originally posted by: Questar

Originally posted by: Regs

Originally posted by: Questar

Originally posted by: A554SS1N
Any reason why AMD would miss out K9 from the architecture naming? I.e. all this talk abut K10 being the name doesn't make sense?

The K9 project was killed in the summer of 2003 - Google it to find the exact date.

Remember, this chip is not K10, it's a spin of K8.

Says who? The die has been drastically altered. The cache hierarchy has been changed. It works on a different socket. It will be the first native quad core design. As for IPC advancements, only AMD knows. Though what I said so far should draw the line clear enough that this is no spin off the K8.

Actually I think AMD is dropping the k# labelling all together. Barcelona is the name they gave it.

Says Who?

AMD. Phil Hester to be exact.

No, he didn't...if you are referring to the interview from last march, then it was Digitimes that called it K8L. He went along with it and spun an "evolution not revolution" marketing story from it.

Edit: BTW, I found something I can actually print (since I didn't source it) confirming this...
Text

Again, AMD has explicitly told me its native quad-core chips will be K10, not K8. That's from their Technical Director - Sales and Marketing EMEA, so isn't likely to be wrong.

James Morris
consultant editor - HEXUS.net

 

[Nemesis 1]

Penryn yorkfield will be up to 150% faster than C2Q/ Links are posted in the penryn up and running thread.

 

[Acanthus]

Once you sift through the marketspeak, it doesnt seem like there are any tangible numbers there that translate to real world performance.

And to top it off, they wont be up against clovertown by the time they get this thing out, theyll be up against 45nm.

 

[Viditor]

Originally posted by: Acanthus
Once you sift through the marketspeak, it doesnt seem like there are any tangible numbers there that translate to real world performance.

And to top it off, they wont be up against clovertown by the time they get this thing out, theyll be up against 45nm.

Ummm...Barcelona will be available in Q2 of this year, 45nm from Intel will be available in Q1 08, and we still don't know when the Xeon versions will be released.

The only tangible numbers would be the 80% increase in FP over current Opterons at the same clock on a core for core basis...
If you extrapolate that to current comparisons and remember that even current Opterons scale much better than Cloverton, a 40% edge is not improbable...
That said, I agree with the "skeptical" sentiment...show me!

 

[Viditor]

Originally posted by: Nemesis 1
Penryn yorkfield will be up to 150% faster than C2Q/ Links are posted in the penryn up and running thread.

Could you repost them?
I couldn't find anything that said that...

 

[Nemesis 1]

Originally posted by: Viditor

Originally posted by: Nemesis 1
Penryn yorkfield will be up to 150% faster than C2Q/ Links are posted in the penryn up and running thread.

Could you repost them?
I couldn't find anything that said that...

If you read this.

http://www.intel.com/technology/magazine/research/speculative-threading-1205.htm

The Mitosis system has been designed to optimize the trade-off between software and hardware to exploit speculative thread-level parallelism.

The Results
To illustrate the performance potential of the Mitosis compiler, let's look at a subset of the Olden benchmark suite. Olden benchmarks are pointer-intensive programs that make it difficult for automatic parallel compilers to extract any thread-level parallelism.


Figure 3. In this graph, the blue bars show the performance improvement going from an in-order to an out-of-order
core with about twice the amount of resources. The red bars indicate the performance of a processor with perfect
memory, illustrating the potential performance improvement for any technique that targets simply reducing memory latency. The yellow bars show the performance gains that result when using Mitosis with a four-core processor.

The results obtained by the Mitosis compiler/architecture for this subset of the Olden benchmarks are very encouraging, outperforming single-threaded execution by 2.2x. When compared with a big out-of-order core, the speed increase is close to 2x. One can also see that the benefits of Mitosis do not come only from reducing memory latency?using Mitosis enables the system to outperform an ideal system with perfect memory by about 60 percent. Overall, this work demonstrates that significant amounts of thread-level parallelism can be exploited in irregular codes, with a rather low overhead in terms of extra (wasted) activity.