AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[witeken]

Those Zen SKUs start at quite the price .

 

[turtile]

But i really dont understand why they will not be able to make a 6 Core SKU, why they will not be able to disable 2 Cores from the CCX ??

Each unit has 4 cores that share an L3 cache. I'd assume having 2 cores sharing an L3 while the other 4 shared an equivalent L3 would mess things up.

 

[AtenRa]

Whether there is a limitation here or not I do not know, maybe others can chime in and help. However, the same prediction still applies to 6C/12T instead of 8C/8T, with a small throughput difference (and a price tad lower to match). It does appear to me though that as long as yields permit, 8C/8T makes more sense financially than 6C/12T while being close enough performance wise to not warrant doing both.

Personally i would go for

4C 4T at $179
4C 8T at $219
Compete against unlocked Core i3 and entire Core i5 family

6C 6T at $279
6C 12T at $319
Compete against Core i7 4C 8T KBL family

8C 8T at $379
8C 16T at 499
Compete against 6C 12T HEDT Intel

 

[AtenRa]

Each unit has 4 cores that share an L3 cache. I'd assume having 2 cores sharing an L3 while the other 4 shared an equivalent L3 would mess things up.

You can disable two cores and half the cache, i dont see any problem with that.

4 Cores active in one unit with entire L3 cache + two cores active with half the L3 cache in the next unit.

 

[turtile]

You can disable two cores and half the cache, i dont see any problem with that.

4 Cores active in one unit with entire L3 cache + two cores active with half the L3 cache in the next unit.

But that would still change performance since the L3 is shared. So one core could still obtain more data from the L3 fom the 4 core cluster as opposed from the 2 core with half of the L3 gone.

 

[Ancalagon44]

AMD has done similar things before - disabling cores but leaving all of the L3 cache intact.

I wonder how many different Zen dies they are manufacturing? I mean, is there a 4 core die and an 8 core die? Or are they just going to disable cores and L3 cache to make 4 core chips to sell?

I also wonder what the lowest SKU will be? I don't think there will be any dual core Zen SKUs. But then the whole SR3, SR5 and SR7 naming scheme makes little sense, since none of those numbers corresponds to core or thread count. I suppose they want names that consumers can easily compare to the Intel equivalent?

My guess is that the SR3 - or the lowest SKU, whatever that is - will be a 4C 4T part. Possibly no L3 cache.

 

[AtenRa]

But that would still change performance since the L3 is shared. So one core could still obtain more data from the L3 fom the 4 core cluster as opposed from the 2 core with half of the L3 gone.

Well you either leave the same cache in each unit or you can cut it in half, it can be done, Intel done it before so i dont see why it should be a problem.
Even if two cores have more L3 cache available than the other 4 in the next unit i dont really see whats the problem, there might be one time that one core will be faster than the other core. Well thats happening all the time is every Multi-Core CPU, not all threads finish at the same time.

 

[bjt2]

Each unit has 4 cores that share an L3 cache. I'd assume having 2 cores sharing an L3 while the other 4 shared an equivalent L3 would mess things up.

It seems that each core comes with an L3 slice of 2MB at same clock... Like INTEL, but with bi-star topology, instead of ring topology. Probabily disabling a core, disables only the L3 slice attached to it...

The situation is even simpler than on INTEL CPUs. On INTEL, disabling a core require (i hope and i guess, for the sake of latency) a bypass on the core slot, to let data pass through... On AMD, since is a star topology, simply that branch will never see a bit through it...

 

[TheELF]

Not happening, what you saying doesnt make financial sense. There is no way AMD will loose 4 Cores 8 Threads if there is a defect in just one of the Cores per CCX. Even on Bulldozer (CMT) we could disable one core inside each Module. Im pretty certain they can desable 2 Cores if needed per CCX to create a 6C 12T SKU.

Also, what if you have a defect in 1 core per each CCX ??? you loose the entire die ??? not happening, they will be able to disable Cores within each CCX.

As I said before,they might do this at some time but if one of the release skus is 6core they have huge yield problems.

If they already have that many defective units to make SKU's based on them that long before launch then they have big big huge gigantic problems.
Sure some months after release it would make sense if they gathered enough defective dies but not pre release.

 

[jpiniero]

It sounds like the top model is the only one that will be available initially.

 

[AtenRa]

As I said before,they might do this at some time but if one of the release skus is 6core they have huge yield problems.

No that doesnt mean they have yield problems, they sacrifice 2 Cores to create a 6C 12T SKU because they actually dont have a 6C 12T die.
Its called segmentation, you have one die to feel 2-3 segments. Some dies may be with defects, but you also have to disable cores from good dies as well in order to fill the market.
You save time and resources from creating 2-3 different dies by creating a single 8C 16T die and then you start to disable cores to create different SKUs.

 

[TheELF]

No that doesnt mean they have yield problems, they sacrifice 2 Cores to create a 6C 12T SKU because they actually dont have a 6C 12T die.
Its called segmentation, you have one die to feel 2-3 segments.

Yeah,or you could just put the chipset and the bios on the die and do your segmentation by limiting clocks,much less wastefull,much more profit.

 

[AtenRa]

Yeah,or you could just put the chipset and the bios on the die and do your segmentation by limiting clocks,much less wastefull,much more profit.

You will again have to sell a 180-200mm2 die for $200 and also, nobody will buy a 8C 16T with 2GHz clocks for desktop.
But they would buy an unlocked 4C 8T SKU for $200-230 or 6C 12T for $300-320 etc.

Intel sells a 120-130mm2 die (4C 8T + GT2) from $180 (i5 4C 4T) up to $350 (i7 4C 8T). AMD can do the same here, why do you react like its something new ??

 

[TheELF]

You will again have to sell a 180-200mm2 die for $200 and also, nobody will buy a 8C 16T with 2GHz clocks for desktop.

The 8c/16t zen is not supposed to be a desktop CPU.

 

[AtenRa]

The 8c/16t zen is not supposed to be a desktop CPU.

They will sell them in the desktop market much like Intel sells those HEDT CPUs in desktop.

 

[Doom2pro]

No that doesnt mean they have yield problems, they sacrifice 2 Cores to create a 6C 12T SKU because they actually dont have a 6C 12T die.
Its called segmentation, you have one die to feel 2-3 segments. Some dies may be with defects, but you also have to disable cores from good dies as well in order to fill the market.
You save time and resources from creating 2-3 different dies by creating a single 8C 16T die and then you start to disable cores to create different SKUs.

AMD did this with Phenom II's especially the business models, and quite a few of them had perfectly functioning cores that could be unlocked through the BIOS on supporting motherboards. I have a machine in my bedroom that has a "Dual Core" Phenom II (B59) that unlocks to a Quad Core Phenom II with all the cores functional including cache (it is equivalent to a Phenom II X4 965C3 Rev).

 

[swilli89]

The 8c/16t zen is not supposed to be a desktop CPU.

No.. that's.. not correct at all.

 

[Doom2pro]

No.. that's.. not correct at all.

He must have misspoke, I mean AMD has said all along they intend the first Zen parts to be 8C/16T HEDT... Emphasis on DT.

 

[LTC8K6]

Yeah,or you could just put the chipset and the bios on the die and do your segmentation by limiting clocks,much less wastefull,much more profit.

They are supposed to be unlocked and overclock friendly, though.

Limiting clocks doesn't sound friendly.

 

[LTC8K6]

He must have misspoke, I mean AMD has said all along they intend the first Zen parts to be 8C/16T HEDT... Emphasis on DT.

Yes, I think that is correct. I recall wondering about that plan, given the size of the HEDT market.

 

[TheELF]

He must have misspoke, I mean AMD has said all along they intend the first Zen parts to be 8C/16T HEDT... Emphasis on DT.

Look at intel's HEDT offerings,all much lower clocked then "normal" desktop parts...
http://www.intel.com/content/www/us/en/processors/core/core-i7ee-processor.html

Why?Because people buy those for semi professional workloads where the amount of cores is way more important then their speed.

 

[LTC8K6]

Look at intel's HEDT offerings,all much lower clocked then "normal" desktop parts...
http://www.intel.com/content/www/us/en/processors/core/core-i7ee-processor.html

Why?Because people buy those for semi professional workloads where the amount of cores is way more important then their speed.

I actually don't think they are far enough off of the desktop offerings to be significant.

Broadwell desktop was not clocked high at all. Broadwell E is pretty much clocked in the same ballpark.

Haswell has an oddball chip clocked very high, the Devil's Canyon 4790K with a 4.0 base clock. Throw that out, and the clock speeds aren't so slow for the Haswell E chips.

We have not seen the Skylake HEDT chips.

 

[moonbogg]

If the 8/16 chip is priced around $500, that should mean the skylake 8/16 chip comes in under $1000. If it doesn't, then maybe an 8 core Zen would be more attractive to a lot of people. I hope AMD forces prices down because Intel's 8 & 10 core chips are stupidly expensive. If Zen OC's at least decently well, they will sell like hotcakes I'm thinking. I can see lots of gamers with Zen 6 core rigs for a good price.

 

[Fanatical Meat]

I just hope AMD has some reasonable control over their motherboard partners. I've had nothing but bad luck from their MB makers but I'll admit I was playing in the value segment but multiple failures on two different vendors boards is hard to justify.

 

[USER8000]

AMD has done similar things before - disabling cores but leaving all of the L3 cache intact.

I wonder how many different Zen dies they are manufacturing? I mean, is there a 4 core die and an 8 core die? Or are they just going to disable cores and L3 cache to make 4 core chips to sell?

I also wonder what the lowest SKU will be? I don't think there will be any dual core Zen SKUs. But then the whole SR3, SR5 and SR7 naming scheme makes little sense, since none of those numbers corresponds to core or thread count. I suppose they want names that consumers can easily compare to the Intel equivalent?

My guess is that the SR3 - or the lowest SKU, whatever that is - will be a 4C 4T part. Possibly no L3 cache.

I expect only one die at launch for consumer parts which is 8C/16T.