AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[LTC8K6]

$220 as the lowest would seem to be well above the price of the i3-7350K chip which is supposedly at $177.

 

[Glo.]

Nah, I don't expect any cores within a CCX to be disabled.

I could see 4C/8T, 8C/8T, and 8C/16T parts.

That is actually very good idea.

 

[LTC8K6]

$220/1500RMB would put the lowest SR chip at the price of the i5-7600, if that KL list is accurate.

 

[KTE]

Arachno: we wish

Sent from HTC 10
(Opinions are own)

 

[swilli89]

That is actually very good idea.

Yes.. I love this stratification. Makes a lot of sense. Now they just need to release the damn things already!

 

[AtenRa]

I didn't say Haswell IPC nor 4GHz overclock capability. Those are sprinkles of magic that you added to the discussion.

Everyone adds something new in the discussion, thats what this forum is all about.

 

[TheELF]

That is actually very good idea.

After the recent news that AMD is searching for "golden chips" I can imagine that 5 and 7 will be the same thing 8c/16t but with very different clocking margins and the 3 part would maybe be 4c/8t.
I mean wasn't SMT supposed to be a part of the whole zen core design?Would seem odd for AMD to release CPUs with disabled features.

 

[KTE]

After the recent news that AMD is searching for "golden chips" I can imagine that 5 and 7 will be the same thing 8c/16t but with very different clocking margins and the 3 part would maybe be 4c/8t.
I mean wasn't SMT supposed to be a part of the whole zen core design?Would seem odd for AMD to release CPUs with disabled features.

It wouldn't seem odd at all if the performance is competitive

Sent from HTC 10
(Opinions are own)

 

[jpiniero]

To me, the chart looked like a pricing range. It's possible they are all 8 core for all we know. People still expect AMD to keep all models unlocked, right?

It wouldn't seem odd at all if the performance is competitive

Define competitive though. I mean I fully expect the top model to be better than the i5 in games just due to the extra cores. I guess the question is what AMD can offer gamers what Intel won't.

 

[nismotigerwvu]

FWIW I'm hearing good news but... I'm not sure how much to say because the person is biased.

From what I'm hearing this is well worth the wait. Unlike anything since AMD 2005.

I'll catchup on posts later at the weekend.

Sent from HTC 10
(Opinions are own)

2005 might be a bit of a stretch. While it never competed for the performance crown, the Phenom II (and 45nm Stars cores in general) gave some terrific bang for the buck and had a few easily recommendable SKUs in their day. Hell, Conroe didn't launch until August 2006 so AMD was still eating Intel's lunch for more than half of that year too anyways. Also, I know I'm taking this WAY too literally and trust me, I'd like nothing more than some competition on the high end once again too.

 

[Doom2pro]

After the recent news that AMD is searching for "golden chips" I can imagine that 5 and 7 will be the same thing 8c/16t but with very different clocking margins and the 3 part would maybe be 4c/8t.
I mean wasn't SMT supposed to be a part of the whole zen core design?Would seem odd for AMD to release CPUs with disabled features.

So why can't AMD harvest defective dies and release 8C8T, 4C4T parts to turn defective throwaway dies into profitable mid range SKUs?

 

[jpiniero]

So why can't AMD harvest defective dies and release 8C8T, 4C4T parts to turn defective throwaway dies into profitable mid range SKUs?

HT probably isn't big enough to make a difference in yield I imagine. Cache yes. I suppose that would be one option for AMD; disable some of the cache on both clusters and disable HT for marketing reasons. So you could have 8C16T, 8C8T with some cache cut. And then 4C8T fully enabled but only one cluster.

 

[TheELF]

So why can't AMD harvest defective dies and release 8C8T, 4C4T parts to turn defective throwaway dies into profitable mid range SKUs?

If they already have that many defective units to make SKU's based on them that long before launch then they have big big huge gigantic problems.
Sure some months after release it would make sense if they gathered enough defective dies but not pre release.

 

[Doom2pro]

HT probably isn't big enough to make a difference in yield I imagine. Cache yes. I suppose that would be one option for AMD; disable some of the cache on both clusters and disable HT for marketing reasons. So you could have 8C16T, 8C8T with some cache cut. And then 4C8T fully enabled but only one cluster.

I have heard SMT is quite a power & space liability, so I don't see how significant quantities can't be effected by defects, obviously not as much as something as large as L3 but significant none the less.

Obviously 14LPP is a new node, and eventually they will be baking quite a few of these 8C16T designs, after ramp up and volume production, defects start to add up, and they can supplement them with additional crippling.

Is there any evidence of a smaller design used specifically for the 4C8T SKUs they are confirmed to be producing? Or are they using defective 8C16T dies or intentionally neutering them to get decent stock?

We all know cheaper SKUs sell more than expensive ones, otherwise the practice of neutering dies wouldn't be commonplace.

 

[jpiniero]

Is there any evidence of a smaller design used specifically for the 4C8T SKUs they are confirmed to be producing? Or are they using defective 8C16T dies or intentionally neutering them to get decent stock?

There's only one Summit Ridge die, with 8 cores. How they cut it is up to them, and of course what GloFo can produce.

 

[sirmo]

HT probably isn't big enough to make a difference in yield I imagine. Cache yes. I suppose that would be one option for AMD; disable some of the cache on both clusters and disable HT for marketing reasons. So you could have 8C16T, 8C8T with some cache cut. And then 4C8T fully enabled but only one cluster.

Don't really think disabling HT helps the yield that much if at all. Intel disables it just for product segmentation. Intel also disables some virtualization features on the K chips.. which I always found really annoying. AMD to my knowledge doesn't cripple features when binning, only the yield related stuff, like disabling full cores.

 

[itsmydamnation]

its worth considering the idea that all partial ccx failure chips will be server SKU's so they can hit 12/24 core server chips without wasting good 8 core dies. only in the case of a complete CCX failure will you see 4 core consumer zeppelins.

 

[biostud]

AMD is going with sr7, sr5 and sr3

https://www.computerbase.de/2016-11/amd-zen-sr7-sr5-sr3

https://www.chiphell.com/thread-1670005-1-1.html

 

[Thunder 57]

After the recent news that AMD is searching for "golden chips" I can imagine that 5 and 7 will be the same thing 8c/16t but with very different clocking margins and the 3 part would maybe be 4c/8t.
I mean wasn't SMT supposed to be a part of the whole zen core design?Would seem odd for AMD to release CPUs with disabled features.

Right, because Intel has never sold chips with SMT disabled or less cache...

 

[coercitiv]

8C 8T at $300 with Ivy-Haswell IPC and more than 4GHz OC capability will certainly stir the x86 Desktop waters.

Going against 4C/8T KBL might seem like overkill, but there are a number of factors that we should take into account:

• When talking overclocks, consider 4Ghz vs 5Ghz. Stock clocks will likely be in the realm of 3.6Ghz vs 4.5Ghz, this 20-25% clock advantage is likely to be preserved. (Zen is still 8C, even w/o SMT)
  
• Skylake arch will have a 8%-15% IPC advantage even with an optimistic Ivy-Haswell IPC mix on Zen.
  
• Unless memory controller on Zen is top notch, a few percent of performance will be squeezed out of there as well.

So, in up to 4 threaded scenarios, KBL will still have quite an advantage (potentially still in "huge" territory, but AMD better have some kind of decent power management capable of boosting clocks when power is not an issue - their mobile XV APU efforts should pay off here). As you move towards more threads things will start looking better for Zen, ending up with a potential 8/7 throughput ratio in favor of AMD. This will likely be their selling proposition.

Finally, AMD needs to offer more than the competition in the same price range. Even if by some celestial miracle Zen is in Haswell+ territory, they still need to offer "more" to the consumer in order to make a compelling proposition. In my view Zen will be a "buy 6 threads get 2 for free" kind of offer, and I say that with no disrespect since it may actually be quite a deal in the end.

Don't expect Zen 8C/8T oc to be a hands down winner in gaming against KBL 4C/8T. Expect a lot of controversy, with emphasis on current titles for Intel, platform flexibility/longevity for AMD. Ironically the same argument is being made constantly right now on the forum when talking about i7 stock versus i5 oc. (i5 oc fine now, but will come crashing down in years to come).

Let the War of the Eight Threads begin!

 

[AtenRa]

Going against 4C/8T KBL might seem like overkill, but there are a number of factors that we should take into account:

• When talking overclocks, consider 4Ghz vs 5Ghz. Stock clocks will likely be in the realm of 3.6Ghz vs 4.5Ghz, this 20-25% clock advantage is likely to be preserved. (Zen is still 8C, even w/o SMT)
  
• Skylake arch will have a 8%-15% IPC advantage even with an optimistic Ivy-Haswell IPC mix on Zen.
  
• Unless memory controller on Zen is top notch, a few percent of performance will be squeezed out of there as well.

So, in up to 4 threaded scenarios, KBL will still have quite an advantage (potentially still in "huge" territory, but AMD better have some kind of decent power management capable of boosting clocks when power is not an issue - their mobile XV APU efforts should pay off here). As you move towards more threads things will start looking better for Zen, ending up with a potential 8/7 throughput ratio in favor of AMD. This will likely be their selling proposition.

Finally, AMD needs to offer more than the competition in the same price range. Even if by some celestial miracle Zen is in Haswell+ territory, they still need to offer "more" to the consumer in order to make a compelling proposition. In my view Zen will be a "buy 6 threads get 2 for free" kind of offer, and I say that with no disrespect since it may actually be quite a deal in the end.

Don't expect Zen 8C/8T oc to be a hands down winner in gaming against KBL 4C/8T. Expect a lot of controversy, with emphasis on current titles for Intel, platform flexibility/longevity for AMD. Ironically the same argument is being made constantly right now on the forum when talking about i7 stock versus i5 oc. (i5 oc fine now, but will come crashing down in years to come).

Let the War of the Eight Threads begin!

Im thinking about in the same lines, KBL will still have the highest IPC and highest ST performance (perhaps even higher OC clocks) so AMD will have to give more for less. But this time they will not be in such a bad position, not in Performance, not in power and not in die cost economics.

But i really dont understand why they will not be able to make a 6 Core SKU, why they will not be able to disable 2 Cores from the CCX ??

 

[TheELF]

But i really dont understand why they will not be able to make a 6 Core SKU, why they will not be able to disable 2 Cores from the CCX ??

Because 4 cores are one unit,if they have dies where one unit is defective they can still sell them as 4c/8t at a profit
,if they disable 2 cores from a fully functional two unit die they are loosing money.
http://wccftech.com/amd-zen-x86-quad-core-unit-block-diagram/

 

[coercitiv]

But i really dont understand why they will not be able to make a 6 Core SKU, why they will not be able to disable 2 Cores from the CCX ??

Whether there is a limitation here or not I do not know, maybe others can chime in and help. However, the same prediction still applies to 6C/12T instead of 8C/8T, with a small throughput difference (and a price tad lower to match). It does appear to me though that as long as yields permit, 8C/8T makes more sense financially than 6C/12T while being close enough performance wise to not warrant doing both.

 

[Dresdenboy]

Don't expect Zen 8C/8T oc to be a hands down winner in gaming against KBL 4C/8T. Expect a lot of controversy, with emphasis on current titles for Intel, platform flexibility/longevity for AMD. Ironically the same argument is being made constantly right now on the forum when talking about i7 stock versus i5 oc. (i5 oc fine now, but will come crashing down in years to come).

That heavily depends on thread utilization and correlation between gaming performance (DX11, DX12+) with our only two main performance guidances for Zen (aside from uarch details): IPC and clock frequencies.

Some gaming benchmarks don't look that bad even on IVB-E or BDW-E compared to SKL, even with the latter having a ST performance advantage. Other factors might be more important here (e.g. thread utilization, cache latencies, aggregate cache size, etc.). So IPC*f might not tell the whole story.

Further with games using more and more threads (more than 4 seems to become standard with some engines), there is an interesting effect when running them on non-SMT machines vs. SMT machines, as in a SMT machine, 2 threads on a core will each run on average at roughly 65% the speed of a single thread on that core, causing longer render/processing times for the individual thread time slices.

So a 8C/8T vs. 4C/8T situation with significantly higher ST performance of the latter might not turn out to be a clear win for it.

 

[AtenRa]

Because 4 cores are one unit,if they have dies where one unit is defective they can still sell them as 4c/8t at a profit
,if they disable 2 cores from a fully functional two unit die they are loosing money.
http://wccftech.com/amd-zen-x86-quad-core-unit-block-diagram/

Not happening, what you saying doesnt make financial sense. There is no way AMD will loose 4 Cores 8 Threads if there is a defect in just one of the Cores per CCX. Even on Bulldozer (CMT) we could disable one core inside each Module. Im pretty certain they can desable 2 Cores if needed per CCX to create a 6C 12T SKU.

Also, what if you have a defect in 1 core per each CCX ??? you loose the entire die ??? not happening, they will be able to disable Cores within each CCX.