AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[ksec]

Speaking of Fottemberg and TSMC and GloFo tapeouts: http://semiaccurate.com/forums/showpost.php?p=276505&postcount=4162

I hope this is true, AMD is too bad, it is just GloFlo lacking behind all the time. From Tech to yield.

 

[Dresdenboy]

Porting an extremely complex design such as Zeppelin to a completely different process, just for a single purpose makes very little sense no matter how you look at it. Not that I would complain if such swap would be made though.

Zen+ maybe. But to be able to base this development on a safe decision regarding process, the GloFo negotiation might have been too late.

 

[KTE]

^It is possible that they've already formed something in agreement allowing it IF GloFo can't deliver the volume, performance and yields needed -- as a safeguard.

But I still cannot see it just to make OC versions.

This net is really full of so much bs.


Sent from HTC 10
(Opinions are own)

 

[majord]

Funny thing about the "on package bios", "which takes 30 minutes to reset".

I know as a fact that the bios on these systems is not located on chip, but on the motherboard as usual. It would be impossible to have the bios located inside the CPU, since different boards require different code depending on their configuration. The bios contains initialization code & firmwares for the external peripherals, such as storage, network, audio, etc controllers and in some cases programming parameters for the VRM controller. Not to mention that nowdays most of the ODMs have proprietary functions in their bioses (such as tuning features).

So unless AMD plans to pre-program the CPUs to work only in a specific board model, or alternatively the ODMs plan to bundle the CPUs with their boards... well, make your own conclusions.

Zeppelin uses a new AGESA core version, but the basic layout & functionality is still the same as on previous platforms. Most, if not all boards will be using Aptio V bios from AMI.

Zeppelin does have a tiny ROM "on die", however it doesn't store anything bios related and there certainly is no need ever to "reset" it.

Also the SMU stands for "System Management Unit", it is not the abbreviation for AMD's SMT implementation like the "source" claims it to be. SMU is the "master of the puppets" on recent GPU ASICs and APUs / SoCs since Trinity. You've seen me talking plenty about the SMU in the past.
At least for now the multithreading implementation goes by it's original abbreviation, SMT.

Well on top of all that we know Bristol ridge doesn't have this magical on chip BIOS scheme, yet both share the same platform.

 

[itsmydamnation]

If anything the payments amd made to glofo would be about allowing Zen to be fabbed at samsung based on demand. People are getting caught up in the wishfull thinking of Zen competing with quadcore *lake in absolute ST performance. If Zen delivers it will be server demand filling the Fab's.

AMD's 4 Zepplin SOC helps against one of intels best advantages , building high clocking low variance 500mm+ CPU's and the power/clock scaling in nowhere near the same issue for server parts thax to the low TDP per core.

 

[bjt2]

Funny thing about the "on package bios", "which takes 30 minutes to reset".

I know as a fact that the bios on these systems is not located on chip, but on the motherboard as usual. It would be impossible to have the bios located inside the CPU, since different boards require different code depending on their configuration. The bios contains initialization code & firmwares for the external peripherals, such as storage, network, audio, etc controllers and in some cases programming parameters for the VRM controller. Not to mention that nowdays most of the ODMs have proprietary functions in their bioses (such as tuning features).

So unless AMD plans to pre-program the CPUs to work only in a specific board model, or alternatively the ODMs plan to bundle the CPUs with their boards... well, make your own conclusions.

Zeppelin uses a new AGESA core version, but the basic layout & functionality is still the same as on previous platforms. Most, if not all boards will be using Aptio V bios from AMI.

Zeppelin does have a tiny ROM "on die", however it doesn't store anything bios related and there certainly is no need ever to "reset" it.

Also the SMU stands for "System Management Unit", it is not the abbreviation for AMD's SMT implementation like the "source" claims it to be. SMU is the "master of the puppets" on recent GPU ASICs and APUs / SoCs since Trinity. You've seen me talking plenty about the SMU in the past.
At least for now the multithreading implementation goes by it's original abbreviation, SMT.

I remember that the BIOSes are modular: a network controller with netboot, a SCSI controller has their own BIOSes, that is called after regular BIOS for their initialization... If a MB requires its own code for some custom additional chip (e.g. additiona SATA controller), this can be put on an external on board ROM, called by the master BIOS.
EDIT: and the AMD BIOS can manage also the optional AMD SB, as the 350... So an external BIOS will be needed only for additional SATA, SCSI controller... I don't see this as a big problem...

The advantage of this scheme is that the internal CPU devices, are managed by AMD itself: its code, its responsibility. BIOS and UEFI are standards. If both AMD and the MB manufacturer will comply to the rules, i don't see problems.
Another advantage is price: if a MB manufacturer wants, it can produce a board without additional controllers and even without BIOS chip and traces. I think that only the CMOS battery will be needed on board (we can even verify this if there is an AM4 pin assignment table and there is some Vcmos pin or similar). In this case all BIOS testing is on AMD shoulders and the MB manufacturer must take care only of electrical compliance. Such a board can cost lower than 40$...

This is a good indication. Some months ago I wrote that AMD isn't honest to us about their failed 2016 target, it seems even worse than I thought. This is what they called on track, they lied

So negative news are true (March 2017) and positive news are false? Yeah... I saw this coming...

If anything the payments amd made to glofo would be about allowing Zen to be fabbed at samsung based on demand. People are getting caught up in the wishfull thinking of Zen competing with quadcore *lake in absolute ST performance. If Zen delivers it will be server demand filling the Fab's.

AMD's 4 Zepplin SOC helps against one of intels best advantages , building high clocking low variance 500mm+ CPU's and the power/clock scaling in nowhere near the same issue for server parts thax to the low TDP per core.

Was not the deal about producing also on other foundries (TSMC)? I remember that the deal was about to break the exclusivity...

 

[jpiniero]

Was not the deal about producing also on other foundries (TSMC)? I remember that the deal was about to break the exclusivity...

I think so but I had thought it was about future nodes though; ie: TSMC 7 nm.

 

[The Stilt]

Well on top of all that we know Bristol ridge doesn't have this magical on chip BIOS scheme, yet both share the same platform.

Indeed

 

[KTE]

If anything the payments amd made to glofo would be about allowing Zen to be fabbed at samsung based on demand. People are getting caught up in the wishfull thinking of Zen competing with quadcore *lake in absolute ST performance. If Zen delivers it will be server demand filling the Fab's.

I think so, too.

I think the comparison marketed will be 8core vs 4core. And the extra cores will make it "competitive". Same as Istanbul/Thuban days.

Not anything more.

Sent from HTC 10
(Opinions are own)

 

[Glo.]

Porting an extremely complex design such as Zeppelin to a completely different process, just for a single purpose makes very little sense no matter how you look at it. Not that I would complain if such swap would be made though.

I don't think Fott have meant that there will be one single SKU built on 16 nm FF+ process .

For example, it would be wise to built the lower cost SKUs on GloFo process, and the higher margin ones on TSMC. And the APUs would benefit massively, especially when we consider that they are rumored to use Vega architecture and HBM memory chips. AMD invested some time and money in supply chain and interposer technology for TSMC process.

 

[The Stilt]

NVM, this is futile.

 

[scannall]

I don't think Fott have meant that there will be one single SKU built on 16 nm FF+ process .

For example, it would be wise to built the lower cost SKUs on GloFo process, and the higher margin ones on TSMC. And the APUs would benefit massively, especially when we consider that they are rumored to use Vega architecture and HBM memory chips. AMD invested some time and money in supply chain and interposer technology for TSMC process.

Mark Papermaster has recently said in an interview that HBM is currently too expensive for APU's. While I do think APU's will get HBM eventually, 2017 won't be the year. 2019? Maybe, but it's a wait and see on where the costs go.

 

[The Stilt]

Tested the existing Cinebench versions (R11.5 and R15) on more recent Cinema 4D engines (R17 & R18).

Cinebench R11.5 scene gained nothing (neither ST or MT) from the newer engines, meanwhile the scene from R15 received a nice boost:

R15 = 134 (ST), 2055 (MT)
R17 = 2140 (MT), forgot to test ST
R18 = 157 (ST), 2236 (MT)

Haswell-EP HCC (18C/36T), 3.5GHz (ST), 2.3GHz (MT).

 

[Sweepr]

Naples (Server Zen) SiSoftware Results ''2S1451A4VIHE4_29/14_N''

- Processor Multi-Media: 643.37Mpix/s
- Processor Cryptography (High Security): 0.17GB/s
- Memory Bandwidth: 0.31GB/s
- Processor Financial Analysis (High/Double Precision): 66.75kOPTS

http://ranker.sisoftware.net/show_s...d5e0c6ae93a680f8c5f4d2b7d2efdff98ab786b0&l=en

Here's Xeon E5-2699 v4 in Comparison

- Processor Multi-Media: 941.16Mpix/s - 2458.56Mpix/s
- Processor Cryptography (High Security): 6.50GB/s - 25.08GB/s
- Processor Financial Analysis (High/Double Precision): 149.42kOPTS - 150.32kOPTS

 

[inf64]

Is that SKU 8C/16T? Sisoft is displaying the 4 nodes as 64 threads which is odd if SMT is enabled and SKU is 16C/32T. Base clock is rather low 1.44Ghz, still decent performance.

 

[KTE]

That a 26th October result? The one with bugged mem.

It certainly is a 8C SKU.

Sent from HTC 10
(Opinions are own)

 

[The Stilt]

Is that SKU 8C/16T? Sisoft is displaying the 4 nodes as 64 threads which is odd if SMT is enabled and SKU is 16C/32T. Base clock is rather low 1.44Ghz, still decent performance.

2S1451A4VIHE4_29/14_N is a 32C/64T SKU.

It would be overly optimistic to assume that Sandra can detect anything correctly on these chips. However the nominal clock frequencies of ES parts can be decoded directly from the SKU.

 

[KTE]

2S1451A4VIHE4_29/14_N is a 32C/64T SKU.

It would be overly optimistic to assume that Sandra can detect anything correctly on these chips. However the nominal clock frequencies of ES parts can be decoded directly from the SKU.

The SKU can be right but the details still detected wrong, and cores can be disabled but still read as enabled.

In the mem test, it is read as 8C but 64T.



Sent from HTC 10
(Opinions are own)

 

[Dresdenboy]

The SKU can be right but the details still detected wrong, and cores can be disabled but still read as enabled.

In the mem test, it is read as 8C but 64T.



Sent from HTC 10
(Opinions are own)

Being the one who spotted these first a few days ago, I had some more time to think about them.

There is at least the observation that dies on a MCM might show up as individual nodes. Thus a 4x node sys might be a single chip. The PCI devices could be cross checked via Crashtechs SIV leak at P3DNow.

That 1.44 GHz clock frequency is the same as reported by GB3/GB4 for exactly the same SKU. That makes a true 1.44 GHz somewhat more likely, although I wouldn't expect any strange base clock+multiplier. OTOH the iGPUs already show some odd frequencies.

 

[Glo.]

The scores are good or bad?

 

[jpiniero]

The scores are good or bad?

Good... albeit that Sandra's results are hard to really analyze. It's about 15% faster in the financial analysis test than a single 2698v3, which has half the cores but 40% higher base clock.

 

[Dresdenboy]

The scores are good or bad?

They seem to be held back by something, leading to very mixed results (just ckeck the ranking positions).

 

[inf64]

We won't know for sure until we get some Summit Ridge leaks. Hopefully in December? I personally expect Haswell-E performance level in both ST and MT workloads, which is very very good. Clocks are a big question mark for me though. If stock clocks are comparable to Broadwell-E but OCing fails than the product will be inferior no matter the price difference. if the clocks are lower but it CAN OC high with a high power spike to due to additional Vcore/clocks than it would be a mixed bag.

It has to deliver on all metrics: IPC( below Haswell is a fail), clocks(below Haswell-E is a fail) AND OCing headroom ( 4Ghz is a must).

 

[bjt2]

According to a calculation that I made a while ago (maybe Dresdenboy remember it, as we excanged it over twitter) a 2.4GHz core should draw below 5W, so a 180W 32c 2.4-2.5GHz base clock is feasible...
The ES have low clock for stability tests...

 

[KTE]

According to a calculation that I made a while ago (maybe Dresdenboy remember it, as we excanged it over twitter) a 2.4GHz core should draw below 5W, so a 180W 32c 2.4-2.5GHz base clock is feasible...
The ES have low clock for stability tests...

We have no uarch + process + manufacturing data to model this.

Random guessing aside.

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(Opinions are own)