Indeed, many assumptions are made here, and this is a fairly rough calculation, but the numbers should be in the ballpark.There are so many assumption in that calculation that you have to take those with many grains of salt. The funniest assumption was that of equal yield of 32nm vs. 14nm. And don't forget you have to at least double the price because GloFo also makes a margin on the chips, unless that costs is already factored in in the wafer price, but that is not specified.
And indeed R&D is not included in those costs. For comparison, Intel spends maybe 50% more on R&D than on wafer production, so more of someone's money goes to the development of future products than for the actual production of the product, which is of course necessary for all tech companies to make their business sustainable.
Look at this...
Carrizo gains +100% from Stilt's build. CMT gain drops a little, but for skylake drops very much...
This means the optimized build has nothing to do with 256 bit AVX and it saturates skylake, but not carrizo...
Let's start from this video:
Here is calculated a 2 thread IPC for Zen of 2.22 instructions.
Since the official blender is 128 bit max and most of the instructions are 1 uop, we can safely assume under 2.5 uops/cycle for 2 threads (mean)...
If we assume 75% of these instructions are SSE/AVX 128 and that in the Stilt's build they are transformed in 256 bit and thus occupy 2 uops, we have that the mean IPC for 2 threads of this new build is a little more 4 uops cycle, with 3.8 uops/cycle of broken 256 bit instructions. But Zen FPU can do 4 uops/cycle. So theoretically even Zen can have the +100% increase of carrizo. I don't expect such an increase though, but at least +50% yes. And from the image posted above, skylake gains "only" about 30%...
Do you have the input file and how Handbrake was run? If so I can give you results.
http://www.bitsandchips.it/52-engli...her-than-usual-vcore-during-new-horizon-eventWe don't know the IPC really. We just know Zen is faster in blender. The power consumption is actually roughly the same, as was demonstrated in the demo.
I am hyped too, but let's not go too crazy just yet.
There's this: https://www.reddit.com/r/Amd/commen...ks/db8hpfe/?context=3&st=iwur5a96&sh=ad479dc3Do you have the input file and how Handbrake was run? If so I can give you results.
Thats why I may not be wrong after all in terms of clock speeds .
It was insurance so that the presentation won't turn into a disaster. They're still tweaking things.In that report the rumor troubles me that Ryzen might have needed extra vcore - that's not very promising for a q1 availability.
I would have expected AMD to actually have pretty much final silicon
In that report the rumor troubles me that Ryzen might have needed extra vcore - that's not very promising for a q1 availability.
I would have expected AMD to actually have pretty much final silicon
AMD amended their WSA to be able to fab at Samsung as well. However they have to pay some money to GloFo per wafer even if they use Samsung. So it's really only useful if they can't get enough production out of GloFo.If true we should have chance to see 8C close to 4Ghz, would we?
Does 14nm Zen make by Samsung? I don't think GloFo have enough ability to done this.
I'm sorry, but 98% yield does not pass the sniff test .Indeed, many assumptions are made here, and this is a fairly rough calculation, but the numbers should be in the ballpark.
As for the yields comment, I used a defect density quoted for GloFo's 14nm process a couple of months ago. At said defect density, and assuming Zen is 220mm^2 (Which many calculations point to), you're looking at 97.8% yield. The difference between 32nm and 14nm yields would not change much in the end in terms of manufacturing costs per chip. At this point what they'll change is how many chips can be sold at X bin.
GloFo only takes a margin on the chips if AMD manufactures outside of GloFo. If they use GloFo, they only pay the wafer price as is normal, and even then it wouldn't "double" the price as GloFo's margin isn't THAT enormous.
And finally on the R&D comment, that's the price Intel pays for owning their own fabs. The wafer prices include those R&D costs, and they're spread over all the companies that use the fab, unlike Intel who has to shoulder all of it on its own.
To fab at Samsung, TSMC, or... Intel.AMD amended their WSA to be able to fab at Samsung as well. However they have to pay some money to GloFo per wafer even if they use Samsung. So it's really only useful if they can't get enough production out of GloFo.
I don't think GloFo and Sumsung are different however. Just based on Nvidia's 1050 and 1050ti which were done at Samsung.. they have about similar gains compared to Maxwell and GCN on 28nm bulk.
* First, wafer cost. I will use the wafer cost reported here: http://semiengineering.com/finfet-rollout-slower-than-expected/. So wafer cost is $4800 (assuming 80% utilization).
Note, by the way, that foundries charge a definite cost per wafer, so that might be 2*4800=9600.
WTH? Never in a million years would I think Intel would fab AMD's products. I knew Intel was opening up fabs to fabless ARM companies, but AMD of all companies?To fab at Samsung, TSMC, or... Intel.
The deal between AMD and Intel for IP, may also include a special deal for using Intel fabs for upcoming AMD tech:
Funniest part of the deal: rumored IP license from Intel is 340 mln USD per year. AMD payed GloFo 340 mln USD to get rid of WSA...
Before you will jump out to conclusions: for Intel getting their fabs is also "wanted thing". They would have a company that would buy hardware(wafers) from Intel fabs, thats how Intel could afford next generation hardware faster.
I used this to get my yield numbers. Take it as you will.
Also, what is the "N" supposed to represent? I didn't quite get it.
As for wafer costs, that 6000$ figure is how much it's supposed to cost AMD, not the actual cost of manufacturing for GloFo.
See my edit. GPUs are much easier to do die harvesting, at least that's why common sense tells me, so the effective yields for GPUs could very well be quite larger (but the same trick can obviously also be done with CPUs).Lol...
If anything think about what should be the cost of the 232mm2 Polaris GPU, likely that it s sold at 90$ at most, and Summit Ridge wont cost more to manufacture..
Intel actually has problem with feeding the fabs. They are pushing the higher cost hardware (HEDT, mobile, BGA-socket) to keep revenue, to keep the money stream for feeding the fabs. ANYTHING that would help offload that will be extremely helpful. From that perspective there is no difference if they would be making hardware for themselves, or for anyone else. The wafers are sold. The fabs are kept fed with work. Simple as it can be.WTH? Never in a million years would I think Intel would fab AMD's products. I knew Intel was opening up fabs to fabless ARM companies, but AMD of all companies?
Is this some sort of a ploy for Intel to steal AMD's designs? /s
I put in 14.83 for both die width and die height, changed the wafer diameter to 300mm, and changed the defect density to 0.01.
Okay, I see what your mistake is. You have to be careful with the units. You have taken as die width and height 1.0 mm. But a die of 220mm² is more like 10mm width and 20mm height. If you run it with those numbers, the site gives a 40% yield, which is somewhere between my assumptions.I don't know..
The N is a parameter that reflects the complexity of the process. The book I used for the formulas said that for the 40nm node, it is between 11.5 and 15.5.
Okay, I see what's the problem.I put in 14.83 for both die width and die height, changed the wafer diameter to 300mm, and changed the defect density to 0.01.