There are so many assumption in that calculation that you have to take those with many grains of salt. The funniest assumption was that of equal yield of 32nm vs. 14nm. And don't forget you have to at least double the price because GloFo also makes a margin on the chips, unless that costs is already factored in in the wafer price, but that is not specified.
And indeed R&D is not included in those costs. For comparison, Intel spends maybe 50% more on R&D than on wafer production, so more of someone's money goes to the development of future products than for the actual production of the product, which is of course necessary for all tech companies to make their business sustainable.
Indeed, many assumptions are made here, and this is a fairly rough calculation, but the numbers should be in the ballpark.
As for the yields comment, I used a defect density quoted for GloFo's 14nm process a couple of months ago. At said defect density, and assuming Zen is 220mm^2 (Which many calculations point to), you're looking at 97.8% yield. The difference between 32nm and 14nm yields would not change much in the end in terms of manufacturing costs per chip. At this point what they'll change is how many chips can be sold at X bin.
GloFo only takes a margin on the chips if AMD manufactures outside of GloFo. If they use GloFo, they only pay the wafer price as is normal, and even then it wouldn't "double" the price as GloFo's margin isn't THAT enormous.
And finally on the R&D comment, that's the price Intel pays for owning their own fabs. The wafer prices include those R&D costs, and they're spread over all the companies that use the fab, unlike Intel who has to shoulder all of it on its own.
Carrizo gains +100% from Stilt's build. CMT gain drops a little, but for skylake drops very much...
This means the optimized build has nothing to do with 256 bit AVX and it saturates skylake, but not carrizo...
Why?
Let's start from this video:
Here is calculated a 2 thread IPC for Zen of 2.22 instructions.
Since the official blender is 128 bit max and most of the instructions are 1 uop, we can safely assume under 2.5 uops/cycle for 2 threads (mean)...
If we assume 75% of these instructions are SSE/AVX 128 and that in the Stilt's build they are transformed in 256 bit and thus occupy 2 uops, we have that the mean IPC for 2 threads of this new build is a little more 4 uops cycle, with 3.8 uops/cycle of broken 256 bit instructions. But Zen FPU can do 4 uops/cycle. So theoretically even Zen can have the +100% increase of carrizo. I don't expect such an increase though, but at least +50% yes. And from the image posted above, skylake gains "only" about 30%...
We don't know the IPC really. We just know Zen is faster in blender. The power consumption is actually roughly the same, as was demonstrated in the demo.
I am hyped too, but let's not go too crazy just yet.
I have said before: if 3.4 GHz Is the base clock for 8 core/16T, and other lines: SR3 and SR5, and in SR7 range is more SKUs than only one, then we can expect higher core clocks for Ryzen.
AMD played very good smoke and mirrors game on their presentation. Exciting times ahead.
Before B&C have touted that if 14 nm GloFo process is good the base clock for highest end will be 3.7 GHz with 4.1 GHz turbo. If it will be very good, base clock will be 4 GHz.
In that report the rumor troubles me that Ryzen might have needed extra vcore - that's not very promising for a q1 availability.
I would have expected AMD to actually have pretty much final silicon
In that report the rumor troubles me that Ryzen might have needed extra vcore - that's not very promising for a q1 availability.
I would have expected AMD to actually have pretty much final silicon
In that report the rumor troubles me that Ryzen might have needed extra vcore - that's not very promising for a q1 availability.
I would have expected AMD to actually have pretty much final silicon
It didnt need to, but that s was a demo made by enginers, and they know that if at stock voltage stability is 1 bug/year increasing voltage by 10% will reduce it to 1/10 years, you wouldnt want that the yearly crash occur the very day you re demonstrating the thing..
Anyway if the info is accurate, and it should be so given the source, 3.6GHz base SKUs are guaranted.
AMD amended their WSA to be able to fab at Samsung as well. However they have to pay some money to GloFo per wafer even if they use Samsung. So it's really only useful if they can't get enough production out of GloFo.
I don't think GloFo and Sumsung are different however. Just based on Nvidia's 1050 and 1050ti which were done at Samsung.. they have about similar gains compared to Maxwell and GCN on 28nm bulk.
Indeed, many assumptions are made here, and this is a fairly rough calculation, but the numbers should be in the ballpark.
As for the yields comment, I used a defect density quoted for GloFo's 14nm process a couple of months ago. At said defect density, and assuming Zen is 220mm^2 (Which many calculations point to), you're looking at 97.8% yield. The difference between 32nm and 14nm yields would not change much in the end in terms of manufacturing costs per chip. At this point what they'll change is how many chips can be sold at X bin.
GloFo only takes a margin on the chips if AMD manufactures outside of GloFo. If they use GloFo, they only pay the wafer price as is normal, and even then it wouldn't "double" the price as GloFo's margin isn't THAT enormous.
And finally on the R&D comment, that's the price Intel pays for owning their own fabs. The wafer prices include those R&D costs, and they're spread over all the companies that use the fab, unlike Intel who has to shoulder all of it on its own.
Calculation: What does 1 Zen die cost to AMD in terms of mfg costs (no R&D, marketing, sales, etc.)?
Assumptions:
* First, wafer cost. I will use the wafer cost reported here: http://semiengineering.com/finfet-rollout-slower-than-expected/. So wafer cost is $4800 (assuming 80% utilization). Seems like a fair number to me given I've also seen estimates anywhere from 6k to 12k.
* Die size. I will just take your word for it and take 220mm².
* Defect density of 0.01 per sq cm. I'll just go with it since there's no way to get better numbers here, but if that is the same as 32nm, that sounds very optimistic. 16nm is now 1.5 years old, but only this year did we see bigger dies, and if the yields published by Intel are anything to go by, the final %% yield improvement are very slow. Also note that number only has 1 significant figure. So to see how the model works, I will also rerun the calculation with 0.05 and 0.1 per cm².
* N = 15.5 (for a 40nm process it is 11.5-15.5, but since the complexity of 14nm is just a ton higher, I'll pick the highest number in that range, although who knows it might be even higher.
* Gross margin. TSMC has a gross margin of 50%, which means a wafer costs (1/ (1 - 0.5)) times more than the production wafer cost (say it takes $1 to make a wafer, then TSMC will charge at least $2 to make 50% gross margin). Because GloFo is also a leading edge player, they also need those margins to sustain their business. Note, by the way, that foundries charge a definite cost per wafer, so that might be 2*4800=9600. But if yields are poor, AMD will need more wafers, so AMD will pay for lower yields, not GloFo (at least, that's how TSMC does it, so GloFo probably does it as well).
* Wafer yield = 100% (as opposed to die yield)
----
Cost of IC = (Cost of die + Cost of testing die + Cost of packaging and final test) / Final test yield
But we will ignore those two other costs. So we get.
Cost of die = Cost of wafer / (Dies per wafer × Die yield)
With
Dies per wafer = (Pi × (Wafer diameter/2)^2) / Die area -- (Pi × Wafer diameter) / sqrt(2 × Die area)
Die yield = Wafer yield × 1 / (1 + Defects per unit area × Die area)^N
The second term in the dies per wafer, which is subtracted, is because you try to fit square dies in a round area.
Okay, so that's the theory (formulas taken from Computer Architecture: A Quantitative Approach). Let's do this as scientific as we can and try to get our model as perfect as possible before running the numbers, which might otherwise cause us to tweak our assumptions in certain ways to influence the output number.
So are you happy with those assumption ?
I urge you to first check the assumptions of the model before you do the calculation. Only after we've agreed on the initial assumption we can see what they give and make tweaks if necessary, or maybe see which assumption were wrong. And it's only when we agree on the model, we can agree on the result.
Anyway, since most readers probably just want to see the output numbers, I'll post them in the spoiler. For my part, I just wanted to show how many unknowns there are that influence actual die cost. If wafer production cost is indeed above 6k, that can easily bump the price by 50%. If the defect density is higher or lower, this will also affect the price, etc. But if you don't agree yet, you shouldn't yet look at the numbers . (So I ask you do determine for yourself the N parameter, wafer price parameter and defect density.)
But before I do the calculations, let's just say that I don't expect AMD to have problems with mfg costs. They should make decent margins on the chips, even on the low-end ones, certainly since I don't expect them to start a price war from the get go. (The high-end one are very high margin, so that's no problem at all.) What interested me is just how to get as good an approximation of the die cost as possible, which your 98% yield number did not do.
Dies per wafer: 276 (constant)
Very optimistic (N=11.5, defect density = 0.01, wafer price = 4800).
Die yield 0.7786 (max = 1.0)
Cost of die: 22.34
Cost for AMD: 44.67
Optimistic (N=15.5, dd = 0.01, wp = 4800).
Die yield: 0.7137
Cost of die: 24.37
Cost for AMD: 48.74
Neutral (N=11.5, dd = 0.05, wp = 4800). [Note: I first took N=15.5, but that gave really bad numbers, too bad to be called neutral]
Die yield: 0.3012
Cost of die: 57.74
Cost for AMD: 115.48
Pessimistic (N=15.5, dd = 0.05, wp = 4800).
Die yield: 0.1984
Cost of die: 87.66
Cost for AMD: 175.32
Very pessimistic (N=15.5, dd = 0.1, wp = 6000). [These numbers might line up more with early 2015 costs ]
Die yield: 0.0549
Cost of die: 395.98
Cost for AMD: 791.95
Conclusions
My initial assumption of N = 15.5 seems untenable. On the low end, this can push yields down from 10% (N=11.5) to 5%, a halving. Just to show how these unknown parameters can affect the price substantially.
Furthermore, the wide range of possible assumptions corresponds in just as large a range of possible die costs. From a decent $45 to a ridiculous $800 bucks. More than one order of magnitude difference. Now, we can say that these very pessimistic assumptions must be wrong, but we can't see by how much or which ones.
In any case, I think the most sure correction I can make is that the N parameter probably is not 15.5, but it could be almost anywhere in the initial range. The defect density of 0.1 is also very probably wrong.
My calculations thus seem to show that the *range* of assumptions (N=11.5-15.5, dd=0.01-0.05, wp=4800-6000) all have some merit in the sense that they can result in a die cost that falls under roughly 250 or even 150. Note that AMD probably wants to have margins of 40%, which would make for a retail price over 400, which is untenable.
The last thing my calculations shows is how much improvement can be made by decreasing defect density for those moderate sized dies (let alone big dies), which we saw confirmed with Intel's 14nm problems. It also shows why mobile CPUs are the first to get to a new process node, instead of GPUs. It of course also shows that bigger dies get more expensive in a quadratic fashion.
I do not wish to make further conclusions based on this data.
But just for fun, if we take N=13.5, dd=0.08, wp=6000, we get that an A9 chip (100mm²) in 2015 would have had a 35% yield, 640 dies per wafer and a production cost of 26.79. So Apple would have had to pay $53.57 under those assumptions (which are between my pessimistic and very pessimistic).
Edit: What my calculations do not take into account is the effect of die harvesting, which might or might not substantially reduce the costs by selling partially defect chips as lower end ones.
AMD amended their WSA to be able to fab at Samsung as well. However they have to pay some money to GloFo per wafer even if they use Samsung. So it's really only useful if they can't get enough production out of GloFo.
I don't think GloFo and Sumsung are different however. Just based on Nvidia's 1050 and 1050ti which were done at Samsung.. they have about similar gains compared to Maxwell and GCN on 28nm bulk.
Funniest part of the deal: rumored IP license from Intel is 340 mln USD per year. AMD payed GloFo 340 mln USD to get rid of WSA...
Before you will jump out to conclusions: for Intel getting their fabs is also "wanted thing". They would have a company that would buy hardware(wafers) from Intel fabs, thats how Intel could afford next generation hardware faster.
@witeken cost per wafer is impossible to calculate as there is so many factors at play which we can only guess at this point.
But I will give you this little tidbit which changes things drastically imo. Owners of GloFo also own 10% of AMD, they have people on the board of AMD. I would be highly surprised if AMD wasn't getting a better deal from GloFo than they would get from both Samsung and TSMC.
Success of both companies is in their mutual best interest.
A.) because GloFo has a guaranteed customer in AMD
B.) AMD being successful means more business to GloFo.
If anything think about what should be the cost of the 232mm2 Polaris GPU, likely that it s sold at 90$ at most, and Summit Ridge wont cost more to manufacture..
Funniest part of the deal: rumored IP license from Intel is 340 mln USD per year. AMD payed GloFo 340 mln USD to get rid of WSA...
Before you will jump out to conclusions: for Intel getting their fabs is also "wanted thing". They would have a company that would buy hardware(wafers) from Intel fabs, thats how Intel could afford next generation hardware faster.
WTH? Never in a million years would I think Intel would fab AMD's products. I knew Intel was opening up fabs to fabless ARM companies, but AMD of all companies?
Is this some sort of a ploy for Intel to steal AMD's designs? /s
Okay, I see what your mistake is. You have to be careful with the units. You have taken as die width and height 1.0 mm. But a die of 220mm² is more like 10mm width and 20mm height. If you run it with those numbers, the site gives a 40% yield, which is somewhere between my assumptions. I don't know.. But the sentiment that I've heard is that you can be quite happy already if you have 80% yields.
The N is a parameter that reflects the complexity of the process. The book I used for the formulas said that for the 40nm node, it is between 11.5 and 15.5.
If anything think about what should be the cost of the 232mm2 Polaris GPU, likely that it s sold at 90$ at most, and Summit Ridge wont cost more to manufacture..
See my edit. GPUs are much easier to do die harvesting, at least that's why common sense tells me, so the effective yields for GPUs could very well be quite larger (but the same trick can obviously also be done with CPUs).
WTH? Never in a million years would I think Intel would fab AMD's products. I knew Intel was opening up fabs to fabless ARM companies, but AMD of all companies?
Is this some sort of a ploy for Intel to steal AMD's designs? /s
Intel actually has problem with feeding the fabs. They are pushing the higher cost hardware (HEDT, mobile, BGA-socket) to keep revenue, to keep the money stream for feeding the fabs. ANYTHING that would help offload that will be extremely helpful. From that perspective there is no difference if they would be making hardware for themselves, or for anyone else. The wafers are sold. The fabs are kept fed with work. Simple as it can be.
Okay, I see what your mistake is. You have to be careful with the units. You have taken as die width and height 1.0 mm. But a die of 220mm² is more like 10mm width and 20mm height. If you run it with those numbers, the site gives a 40% yield, which is somewhere between my assumptions. I don't know..
The N is a parameter that reflects the complexity of the process. The book I used for the formulas said that for the 40nm node, it is between 11.5 and 15.5.
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