Yes and no. It can happen that way, but only with a very mature process node which has had its functional and parametric yields optimized to a tight(er) distribution. Which in general is where all process nodes end up once they have been in the hands of the fab engineers for 6-8 quarters, if not sooner.
It is a matter of functional yield and parametric yield. You need both to be high in order for the scenario you spelled out above to become a practical option for sales and marketing management.
But if either is lacking, the fab is dealing with poor functional yields or poor parametric yields (or both), then the scenario you outline above is not going to even be an option for the business. They will simply be struggling to die harvest and bin out anything and everything they can to, and binning will represent more of an electrical reality than an artificial marketing segmentation.
For new products on a new process node, I would not expect a $49 2.5GHz 8core to OC to 3.9GHz and match the top-end SKU unless the parametric yield distribution within the fab is quite tight, such that basically most CPUs could bin-out at 3.9GHz but the company elects to label/sell them for much lower clockspeeds.
But I would expect that to play out if the node in question has been in production for say 2yrs or so.
Center to edge yield distributions are not really that way any more.
Process engineers intentionally optimize the sweet spots so as to yield the most chips per wafer as possible, that means (if anything) making the center a dead zone and killing the few chips located there if in return they can can convert the edge chips into high yielding chips.
Some 10yrs ago, back when fabs were still in the earlier stages of coming to terms with scaling their 200mm process nodes onto 300mm wafers, it was true that the center area (that 200mm footprint) would have far better yields than the outer edge (the 100mm perimeter doughnut).
But that really was a transitional period, a learning curve for process engineers and tool suppliers, that was overcame within the first couple of nodes that were on 300mm (back in the 130nm and 90nm days).
Nowadays if you end up with an bulls-eye yield pattern on your wafer it is a telltale sign that one of your tools is operating out of spec and you better get on top of it. In other words it is the undesired excursion, not the norm.
If your functional yield is so bad that it is impacting the parametric yield then your process node is truly not manufacturable. Not saying it doesn't happen, just saying it is a huge red flag that you have built something (process node wise) that is going to have serious troubles for everyone involved.
Generally speaking, functional yield issues (particles, defects, flakes, missing pattern, blocked etch, etc.) result in die harvesting. Blocking off dead cores, or eliminating redundant memory cells (2MB L3$ instead of 3MB, for example).
That is true and everyone does it, has done it for decades.
However, generally speaking, your parametric yield issues (speed bins, power-consumption, shmoo plot, etc) come down to process variation and process targets. And that means process control (accuracy and precision).
A chip that is clockspeed limited or power-consumption limited because of a physical defect (functional yield issue) is a chip that is going to be a HUGE in-field reliability nightmare.
No company I know of sells those in the logic industry, but they do sell those "walking wounded" chips in the memory business where "IC grade" comes into play. (think dirt-cheap thumbdrives that rarely work, even the first time)
But your Intel's and Samsung's of the SoC world do not want to ship chips that are excursions and fall outside the distribution that was characterized for lifetime reliability attributes. Better to scrap them and not risk the liability.
(this is where the practice of core-unlocking with AMD die-harvested chips is particularly disconcerting, but ignorance is bliss so why be a debbie downer and spoil the party?
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