AMD Raven Ridge 'Zen APU' Thread

[Glo.]

How they are going to archive that exactly? RX470D is over 100W TDP for the GPU alone, you want a 4/8 + RX470 + HBM stack for 95W?? I really dont think that is tecnically possible. MB VRMs might also be a problem, they were already a problem for FM2.

Also i dont think they can offer an APU like that for less than $300, remember that they need to make money at the end of the day. They also have Microsoft and Sony pressure NOT to do something like that, console killer APU for less money than a console? yeah, not gonna happen.

1024 GCN core Vega chip, with HBM2 and 1.2 GHz core clock should be on par with RX 470D, in some games(like Doom, Vulkan).

Why do people believe that APUs with HBM2 would be cheap solution?

 

[coercitiv]

For comparison sake, the Radeon Pro 460 (1024 cores @ 900Mhz) is rated for 35W TDP.

 

[Glo.]

For comparison sake, the Radeon Pro 460 (1024 cores @ 900Mhz) is rated for 35W TDP.

Actually the GPU die itself is rated at 18W of power, because that is what the GPU consumes in MBP 2016. Rest of 35W TDP is consumed by 4 memory chips.

HBM2 memory should consume 4W per memory stack.

 

[maddie]

How they are going to archive that exactly? RX470D is over 100W TDP for the GPU alone, you want a 4/8 + RX470 + HBM stack for 95W?? I really dont think that is tecnically possible. MB VRMs might also be a problem, they were already a problem for FM2.

Also i dont think they can offer an APU like that for less than $300, remember that they need to make money at the end of the day. They also have Microsoft and Sony pressure NOT to do something like that, console killer APU for less money than a console? yeah, not gonna happen.

Two issues here.

1] A full P10 gpu downclocked to achieve the performance level of a RX 470D [28 CU] would need to be run around 950 Mhz. This allows a very low core voltage [.9V ?]. I believe power usage will be much lower than the 100W you claim. I'm assuming you've seen the 14LPP voltage /frequency curves. A single CCX Zen complex @ 2.8 - 3.0 Ghz should need around 25-30W. A single 2 Gb HBM2 stack around 5W.

We would have about 60W remaining for the GPU portion. Even with Polaris, this should be possible. Assuming Vega is more power efficient, why do you see this as impossible?

2] The full Fiji assembly appears to cost $188. This is with a 600mm^2 GPU + 4 stacks 4-Hi HBM + 1000mm^2 interposer.
Do you see a much smaller APU + 1 stack 2-Hi HBM2 + less than half size interposer as costing more? All at much higher production volumes to even further lower costs. I see the cost as substantially lower.

Remember there is no cooling unit or PCB as on a Video card.

TO sm625, it seems we have arrived at similar values

 

[Shivansps]

While i give it may be possible, I still dont think that AMD will piss off two mayor customers by offering console killer APUs.

 

[Tuna-Fish]

Actually the GPU die itself is rated at 18W of power, because that is what the GPU consumes in MBP 2016. Rest of 35W TDP is consumed by 4 memory chips.

There is also a binning difference. You can bet your butt that the MBPs get the lowest-power chips off the line.

 

[The Stilt]

Actually the GPU die itself is rated at 18W of power, because that is what the GPU consumes in MBP 2016. Rest of 35W TDP is consumed by 4 memory chips.

HBM2 memory should consume 4W per memory stack.

Right.
The smaller Polaris 11 (Coruja 50, 14CU) variant made for Apple has TDP target of 35W while the peak power is 65W.
The full Polaris 11 (Coruja 70, 16CU) variant has TDP target of 50W and peak power of 95W.

Neither of these figures include the VRAM power either.

Considering that the RX 460 cannot sustain it's maximum boost clock (1200MHz) at the default 50W TDP target (GPU only), I find it pretty hard to believe that the mobile variant would consume "18W" of power.

 

[The Stilt]

AMD GPU TDP numbers do not include anything else but the GPU power, meanwhile TBP (typical board power) does include everything.

e.g.

RX 460 = TDP 50W, TBP 75W
RX 480 = TDP 110W, TBP 150W

 

[Abwx]

Considering that the RX 460 cannot sustain it's maximum boost clock (1200MHz) at the default 50W TDP target (GPU only), I find it pretty hard to believe that the mobile variant would consume "18W" of power.

Actually that s quite possible because Polaris power/frequency curve is roughly cubic in this range, so from 50W this yield 21W, and likely said 18W considering the lower leakage at 900Mhz (lower voltage and temp).

 

[Atari2600]

If any RR APU has HBCC onboard and working, then it must have HBM2, as HBCC cannot work with system memory bandwidth.

No, no. If the main *graphics* memory pool is in DDR4, it'll just work slower. It'd be no different from a current generation APU working with single channel or dual channel memory arrangements or faster memory speeds.


Now, what AMD *might* do in that instance is add another tier of local cache to the APU - eDRAM or similar. The HBCC hopefully allows for more mixing and matching of memory architecture without needing ground up redesigns.

 

[Glo.]

Right.
The smaller Polaris 11 (Coruja 50, 14CU) variant made for Apple has TDP target of 35W while the peak power is 65W.
The full Polaris 11 (Coruja 70, 16CU) variant has TDP target of 50W and peak power of 95W.

Neither of these figures include the VRAM power either.

Considering that the RX 460 cannot sustain it's maximum boost clock (1200MHz) at the default 50W TDP target (GPU only), I find it pretty hard to believe that the mobile variant would consume "18W" of power.

If you don't believe me, then check out AdoredTV tests on RX 460 declocked to 850 MHz, and specific voltage that AMD touted in their demo of the GPU last year.

If I remember correctly, he was seeing numbers between 15 and 27W of power.

P.S. The GPUs you quote have BIOS TDP(power target) over which they start to throttle, to avoid exceeding it. And it is settled at 35W, for whole GPU package(GPU die+ memory).

 

[T1beriu]

If I remember correctly, he was seeing numbers between 15 and 27W of power.

Corect. But his test was locked at 60FPS, he's not displaying the GPU usage and when the power consumption drops below 18W it's because most of the screen is taken by the skybox.

This is the video we're talking about.

https://youtu.be/-5dJD-fLfk8?t=13m46s

 

[mtcn77]

No, no. If the main *graphics* memory pool is in DDR4, it'll just work slower. It'd be no different from a current generation APU working with single channel or dual channel memory arrangements or faster memory speeds.


Now, what AMD *might* do in that instance is add another tier of local cache to the APU - eDRAM or similar. The HBCC hopefully allows for more mixing and matching of memory architecture without needing ground up redesigns.

How is it in DDR4? HBCC aims streamlined heterogeneous memory usage, therefore you won't be handicapped by where the main memory strobe lies. Granted, AMD has commented they want to manage the software memory in hardware, so all the more reason to HBCC. One thing that has to come with HBCC is Mega-APU project. I think they are scaling good thus far, considering they started with Llano...

 

[Atari2600]

How is it in DDR4?

If AMD were to release a Raven Ridge without HBM*, then the main system memory pool and the graphics main memory pool will be in the same place... your DDR4 DIMMs.


*Of course, as I said above, they could look at alternatives such as including an eDRAM chip on the die.

 

[mtcn77]

If AMD were to release a Raven Ridge without HBM*, then the main system memory pool and the graphics main memory pool will be in the same place... your DDR4 DIMMs.


*Of course, as I said above, they could look at alternatives such as including an eDRAM chip on the die.

HBCC is synonymous to HBM first to be introduced with Vega. AMD would do well to include it with APU because why hold back the APU line up when you can integrate it into the semi-custom refreshes?
I think you are correct in assuming there might be another memory type, but it is too vague for AMD... They haven't ever tried eSRAM whereas they have and will do so further in the case of HBM. It is very key for AMD to keep it in house.
Things that caused Fiji to be expensive was its humongous 1011mm2 interposer with selective filling. APU's don't have to come with that much stuff to consider. In fact only a quarter memory stacks would make its interposer size very contemporary, imo.

 

[otinane]

HBCC is synonymous to HBM first to be introduced with Vega. AMD would do well to include it with APU because why hold back the APU line up when you can integrate it into the semi-custom refreshes?
I think you are correct in assuming there might be another memory type, but it is too vague for AMD... They haven't ever tried eSRAM whereas they have and will do so further in the case of HBM. It is very key for AMD to keep it in house.
Things that caused Fiji to be expensive was its humongous 1011mm2 interposer with selective filling. APU's don't have to come with that much stuff to consider. In fact only a quarter memory stacks would make its interposer size very contemporary, imo.

They own the patent of ZRAM since 2015, which is by far more effective than DRAM. But for some unknown reason they don't implement it in cases like the APU for example.

https://en.wikipedia.org/wiki/Z-RAM

 

[flash-gordon]

They own the patent of ZRAM since 2015, which is by far more effective than DRAM. But for some unknown reason they don't implement it in cases like the APU for example.

https://en.wikipedia.org/wiki/Z-RAM

It's nice, but it's SOI, who is investing in it for long-term? AMD doesn't own fabs to do it for it's own... That's one reason they prefer to focus on open standards like JEDEC.

 

[maddie]

No, no. If the main *graphics* memory pool is in DDR4, it'll just work slower. It'd be no different from a current generation APU working with single channel or dual channel memory arrangements or faster memory speeds.


Now, what AMD *might* do in that instance is add another tier of local cache to the APU - eDRAM or similar. The HBCC hopefully allows for more mixing and matching of memory architecture without needing ground up redesigns.

You're correct.

I took my position by assuming that AMD would not release a high # CU APU if they were not able to feed it enough data.They do seem more focused and competent nowadays. Why make a more costly part for no performance increase?

 

[Atari2600]

I took my position by assuming that AMD would not release a high # CU APU if they were not able to feed it enough data.They do seem more focused and competent nowadays. Why make a more costly part for no performance increase?

I for one hope there will be a balanced high end APU released. That will by default require HBM (or similar) - otherwise it wouldn't be balanced.

Of course, as you come down to the low end of the performance spectrum - dual channel DDR4-3200 would be sufficient to deliver more than acceptable performance.

AMD's problem has been getting OEMs to actually deliver appropriate sub-systems with their APUs. Single channel & slow memory is wholly inappropriate.

If the OEMs f**k it up again with RavenRidge, AMD would do well to commission several laptop builds (with good keyboard, good screen, good memory, good storage) and sell directly via shop.amd.

 

[maddie]

I for one hope there will be a balanced high end APU released. That will by default require HBM (or similar) - otherwise it wouldn't be balanced.

Of course, as you come down to the low end of the performance spectrum - dual channel DDR4-3200 would be sufficient to deliver more than acceptable performance.

AMD's problem has been getting OEMs to actually deliver appropriate sub-systems with their APUs. Single channel & slow memory is wholly inappropriate.

If the OEMs f**k it up again with RavenRidge, AMD would do well to commission several laptop builds (with good keyboard, good screen, good memory, good storage) and sell directly via shop.amd.

The good thing with a HBM2 APU is that the DDR4 memory system would only have to service the CPU [mainly]. 2 CCX Zen has dual channel. You'll probably get most of the performance even if they only use single channel on 1 CCX units.

On the other hand, seeing that a HBM equipped APU would be high end, you'll probably get dual channel anyhow.

Releasing an AMD laptop is a gutsy move. Quite risky in my view, as many OEMs will be pissed, although if you're being screwed anyhow, I guess there's little to lose.

 

[richaron]

The good thing with a HBM2 APU is that the DDR4 memory system would only have to service the CPU [mainly]. 2 CCX Zen has dual channel. You'll probably get most of the performance even if they only use single channel on 1 CCX units.

On the other hand, seeing that a HBM equipped APU would be high end, you'll probably get dual channel anyhow.

Releasing an AMD laptop is a gutsy move. Quite risky in my view, as many OEMs will be pissed, although if you're being screwed anyhow, I guess there's little to lose.

From the APU diagrams I've seen a HBCC GPU will access system RAM with "IF" via the CPU, so I assume even an APU with no local VRAM should have access to the relatively "large" and low latency CPU L3... which may actually make a measurable difference.

 

[Phynaz]

They own the patent of ZRAM since 2015, which is by far more effective than DRAM. But for some unknown reason they don't implement it in cases like the APU for example.

https://en.wikipedia.org/wiki/Z-RAM

Ummm, read what you post. AMD licensed Z-RAM in 2006. After the inventor went bankrupt Micron picked up the patents in 2011. If you ever see Z-RAM in an AMD product, it's at least a decade away. Although considering Micron is an Intel partner and they are busy with 3D-Xpoint, it's pretty safe to assume Z-RAM is a dead technology.

Either way, AMD doesn't own the IP to Z-RAM.

For a fun read go read the posts in this forum when AMD announced their licensing of the technology.

 

[maddie]

From the APU diagrams I've seen a HBCC GPU will access system RAM with "IF" via the CPU, so I assume even an APU with no local VRAM should have access to the relatively "large" and low latency CPU L3... which may actually make a measurable difference.

I would be astonished if 16Mb of cache, irrespective of the speed or latency, makes any measurable difference for APU gaming.

 

[Topweasel]

From the APU diagrams I've seen a HBCC GPU will access system RAM with "IF" via the CPU, so I assume even an APU with no local VRAM should have access to the relatively "large" and low latency CPU L3... which may actually make a measurable difference.

So in Raven Ridge you would basically end up with 8MB of "eSRAM"?

 

[tamz_msc]

Courtesy r/AMD, RR has an entry in SiSoft(German) - http://ranker.sisoftware.net/show_s...ead7e6c0a895a086fec3f2d4b1d4e9d9ff8cb189&l=de