News AMD previews Ryzen 3rd generation at CES

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Apr 27, 2000
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Probably 14LPP. 14 HPC is an "expensive" process designed for higher clocks needed by chips like POWER9. AMD has never taken delivery of 14HPC wafers for anything, to my knowledge.
 
Dec 29, 2015
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It would be a huge upgrade for the consumer if Ryzen 3 8C 16T would give 90% (or more) of Core i9 9900K Gaming performance at 65W TDP and half the price.
Wasn't this pretty much given? Ryzen 2700 is 65W chip. 7nm process will give it 25% performance boost at the same power even without any architectural improvements. So, simply porting Zen1 to 7nm would get you that.

The demo was just the confirmation of what was expected for Ryzen 3rd gen mid range performance. AMD had to show what they thought was the most underwhelming demo without sabotaging themselves, knowing the pre-CES hype and expectations. It turned out that the most underwhelming demo they came up with happened to be their mid-range beating Intel's top of the line. :)
 
Dec 29, 2015
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The IBM one is usually for higher frequency right? Anyone know if higher clocked IO would be better or matter at all?
High frequency should not matter for IO die. What IBM 14HP would provide is the possibility of having eDRAM. Since XBOX One SoC only had 32MB embedded ram and that was enough to handle 1080p, if it has 32MB of eDRAM, it might be enough as a side port memory to support GPU chiplet on a mobile platform.

AMD already stated that AM4 will not have a GPU chiplet. But that does not mean that they won't make a mobile version with a different substrate.
 

Mopetar

Diamond Member
Jan 31, 2011
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The IBM one is usually for higher frequency right? Anyone know if higher clocked IO would be better or matter at all?
I don't think it would matter overly much. Running it at a higher frequency than whatever it's communicating with wouldn't net any additional improvements. For example, the IO bus speed for DDR4 memory would only be around 2 GHz for the fastest memory, and I'm not even sure if people are using that because the CAS latency is usually a lot higher.
 

IRobot23

Senior member
Jul 3, 2017
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I don't think it would matter overly much. Running it at a higher frequency than whatever it's communicating with wouldn't net any additional improvements. For example, the IO bus speed for DDR4 memory would only be around 2 GHz for the fastest memory, and I'm not even sure if people are using that because the CAS latency is usually a lot higher.
I/O is not made only by IMC, all I/O dont run at same freq. IF is hardlinke to IMC, we don't know about IF2 it could be hardlinked to LLC.
 

NostaSeronx

Platinum Member
Sep 18, 2011
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GlobalFoundries 14HP has better I/O capabilities than 14LPP. However, good luck finding cheap SOI FinFET wafers. Since, it is a low volume product from SOITEC.

I want to get this off my chest...
-> SOI FinFET = THICC SOI
-> FD-3D is an extension/superset of PDSOI wafers.
-> SOI FinFET does not use UTBB SOI(FD-2D) wafers.
 

IRobot23

Senior member
Jul 3, 2017
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I am very curious about I/O, particulary IF2 speed and memory latency. AMD kniws that whole internet was talking about high memory latency... I think they fixed it.
 
Feb 23, 2017
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Decoupling it from memclock would be a great start. Whether it then gets tied to cache or clock speed is another matter. Either way, both would be quicker than memclock, reducing latency somewhat.
Of course, it'd push up power draw for it IMO.
 

IRobot23

Senior member
Jul 3, 2017
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I think it is not tied to llc. Power for servers would be to high... So it has to have its own clock. Tied to IMC clock would show to high latency.
 
Nov 6, 2014
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Just for fun, I tried to make my R7 1800x system run at the same total system power as the Zen2 ES demo machine.

Like the demo machine, I have an RX Vega, though mine is Vega FE. I also have some big honking fans on the HSF (NH-D15) which are not standard - Noctua industrialPPC 3000s, running full bore. This includes the stock fan for a D15S which completes the 3-fan configuration. Finally I have the stock system fans for a Rosewill Thor V2. So my system power draw is going to be a little higher just from the fans. The board is x370 Taichi, and I have a 480GB BPX NVMe SSD. I downclocked my DDR4-3333 to DDR4-2666 to match the system RAM configuration.

Underclocking my chip was kind of hard - I had to use the AMD CBS settings, which are a PITA versus the ASRock OC interface. Regardless, I ran CBR15 @ 3200 MHz and turned in a score of 1412. I measured 180W at the wall. In this power range, my PSU averages maybe 89% efficiency (EVGA P2 750W), meaning pre-loss draw was more in the ballpark of 160W. Subtracting all the extra fan power, I figure my power usage was close to the 135W for the ES demo machine.

And all I scored was a measly 1412.

Not sure if I can get any more clockspeed at that power level, but I doubt it.
Interestingly Adored came to the same conclusion that it was a 65W ES at the presentation. Your result of 1412 is almost exactly what a 65W R7 1700 scores at stock.
It basically means that (atleast for cinebench):
a) Zen 2 has higher IPC than believed;
b) TSMC's 7nm brings higher clocks/reduces power consumption more than believed;
c) combination of a and b.

Unless CB is a one off best case scenario for Zen 2 with unusually huge gains in that test.
 

Arzachel

Senior member
Apr 7, 2011
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High frequency should not matter for IO die. What IBM 14HP would provide is the possibility of having eDRAM. Since XBOX One SoC only had 32MB embedded ram and that was enough to handle 1080p, if it has 32MB of eDRAM, it might be enough as a side port memory to support GPU chiplet on a mobile platform.
The IO die is almost exactly the same size as Summit Ridge with both CCX lopped off (~123mm2 vs 213 - 88 = ~125mm2) so I think we we can pretty safely put the eDRAM rumors to rest.
 

Gideon

Senior member
Nov 27, 2007
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The IO die is almost exactly the same size as Summit Ridge with both CCX lopped off (~123mm2 vs 213 - 88 = ~125mm2) so I think we we can pretty safely put the eDRAM rumors to rest.
Considering that there will be no APU-chiplet version, I wouldn't mind a smallish GPU inside the I/O die (at least the decode/encode blocks and at least 2EUs). It would make this CPU a lot easier to market for OEMs and those retail customers who have no need for a standalone GPU. Some software utilizing integrated graphics for GPGPU or the video-encode blocks (such as Adobe suite) would also work better that way. A small GPU would also mean much better battery life in those desktop-replacement laptops like ASUS ROG STRIX (with Ryzen 1700). Not that it matters much in that segment :D
 

Topweasel

Diamond Member
Oct 19, 2000
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IMO, this is packaging and not directly architecture.
Even if nothing being changed I would still consider it a different arch just like I would consider Conroe and Nahelam to be different Arch. If you a fundamentally changing the the whole communication system even for packaging reasons. I think it becomes a different arch.
 

Topweasel

Diamond Member
Oct 19, 2000
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Considering that there will be no APU-chiplet version, I wouldn't mind a smallish GPU inside the I/O die (at least the decode/encode blocks and at least 2EUs). It would make this CPU a lot easier to market for OEMs and those retail customers who have no need for a standalone GPU. Some software utilizing integrated graphics for GPGPU or the video-encode blocks (such as Adobe suite) would also work better that way. A small GPU would also mean much better battery life in those desktop-replacement laptops like ASUS ROG STRIX (with Ryzen 1700). Not that it matters much in that segment :D
Sorry this is really really really really really tiring. I get wanting a APU 8c chip. I think a 80mm chiplet navi as the second chiplet would be a great idea and kind of disappointed if that isn't happening.

But the IO die having any GPU isn't going to happen and everybody hoping it does is in for a huge disappointment and if AMD did pull it off it would upset everyone. We already lose 8 PCIe lanes just so that the socket can support APU's. Even when installing an dGPU, having a APU in the socket kills an additional 8 lanes. For whatever design wins that AMD misses out on by not having an iGPU on desktop Ryzen's. As for Those design wins, for the most part offering a Desktop APU even if its RR and Picasso, they give a integrated base for more power versions with Ryzen 5-7 to eat up the cost of dGPU. But again the main point is the IO doesn't include a GPU and won't and AMD isn't at the point where the volume of CPU's they are shipping are missing out because their only iGPU cpu's are 4c or less.
 

Atari2600

Senior member
Nov 22, 2016
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We already lose 8 PCIe lanes just so that the socket can support APU's.
I think you are misunderstanding the power of the GPU that is being requested.

1 PCIe lane would be entirely adequate to feed it.

Its something for:
- running the OS (great for debug)
- word processing
- spreadsheets
- basic browsing
- text editor
etc

Power is not required (requested).
 

IRobot23

Senior member
Jul 3, 2017
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There will be no APU chiplets on AM4. Where first chiplet APU will arrive are consoles.
Big deal for console... All you need to do is I/O + 4C/8T with iGPU (shared LLC + no I/O) on board or maybe cpu + Gpu separated dies.

current XBOX has 359mm^2 16nm ~ 14nm (remember R7 1800X has 213mm^2 + RX 480 has 232mm^2 and would be cheaper).

If we take 14nm for it ~ 45mm^2 for zen cores 4C/8T + 125+25mm^2 for I/O die + gpu without I/O ~ 250mm^2 (7nm should be near vega VII) more efficient yields and should cost less than 359mm^2 die. We will see.

Maybe AMD will start to make mcm GPU on consoles first.
 

Topweasel

Diamond Member
Oct 19, 2000
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I think you are misunderstanding the power of the GPU that is being requested.

1 PCIe lane would be entirely adequate to feed it.

Its something for:
- running the OS (great for debug)
- word processing
- spreadsheets
- basic browsing
- text editor
etc

Power is not required (requested).
I'd have to check why the 8 lane drop but I thought I remembered it being wiring that is shared with the video outputs. The other are lost because they have no wiring at all because of the sockets support for AM4 and their decision to not go LGA. It isn't as simple as put a 1-3 unit iGPU for remeadial tasks, AM4 is packed a little tight for Zen's possible feature set and no desktop user wants AMD to lose more PCIe just so that people can pretend it's costing them business sales.
 

Tuna-Fish

Senior member
Mar 4, 2011
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There will be no APU chiplets on AM4.
There might be, later. What AMD stated is that there are no APUs in the Matisse lineup that is coming this summer, and that there will be no APU that uses the same IO chiplet as Matisse and just plugs a GPU part into the other free spot.

This is not saying there will never be a chiplet APU.
 

Thunder 57

Senior member
Aug 19, 2007
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Why, gaming performance is going to be by and large more important for most of the people on this forum.
I think you would be surprised. Not to say gaming isn't on many peoples minds here.

EDIT

As for why I agree I am glad to see more AVX2 performance, simple. x265 transcoding.
 
Last edited:

beginner99

Diamond Member
Jun 2, 2009
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But again the main point is the IO doesn't include a GPU and won't and AMD isn't at the point where the volume of CPU's they are shipping are missing out because their only iGPU cpu's are 4c or less.
Fair enough. And a much easier solution they could offer to OEMs is a rebate on CPU + GPU combo from AMD. If you take both from us you get xx% off the normal price.
 
Feb 23, 2017
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I'd have to check why the 8 lane drop but I thought I remembered it being wiring that is shared with the video outputs. The other are lost because they have no wiring at all because of the sockets support for AM4 and their decision to not go LGA. It isn't as simple as put a 1-3 unit iGPU for remeadial tasks, AM4 is packed a little tight for Zen's possible feature set and no desktop user wants AMD to lose more PCIe just so that people can pretend it's costing them business sales.
Whilst I agree with what you're saying, PCIe4 pretty much mpacts the discussion; since most devices are PCIe3 and PCIe4 lanes can be split into 2x PCIe3, then it maybe is less of an issue.
 

Shivansps

Platinum Member
Sep 11, 2013
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About the reserved PCI-E lanes, Zen 1 die had 4 unused pcie lanes on AM4, if the Ryzen I/O die still has the 32 PCI-E lanes they may be able to run a IGP on it, if they are PCI-E 4.0.
 

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