Question AMD Phoenix/Zen 4 APU Speculation and Discussion

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eek2121

Golden Member
Aug 2, 2005
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Ian never stated that slide came from AMD. That slide is not on their investor presentation: PowerPoint Presentation (d1io3yog0oux5.cloudfront.net), nor is it in in their corporate presentation: PowerPoint Presentation (d1io3yog0oux5.cloudfront.net). Furthermore, Dragon Range is not mentioned at all on the AMD website: site:amd.com "dragon range" - Google Search

Seems like Ian either received a fake leak or got the slide from a third-party source. Given that it has a misspelling, I am extremely skeptical of it being real.
 

jamescox

Senior member
Nov 11, 2009
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Who said it was monolithic? Also, that does imply > 16c, since Intel has a '16 core' gaming CPU.

People keep saying chiplets on mobile can't be done. Adaptive IF and other power optimizations would allow chiplets to happen easily.

EDIT: That slide surely can't be from AMD. It has a misspelling.
What is the misspelling? I have seen official slides with misspellings. This could be a leak from an OEM source; perhaps something for laptop makers. They may have been less careful with something that wasn’t meant for wide distribution.

If low power and multiple chiplets are combined, the best way to for is something like EFB rather than IFOP (serdes based) connections. I don’t really see how they would go above 16 unless they did something like make a 16-core APU and then combine 2 of them together for 32-core via EFB or just use one 8 core high power chiplet plus one 16 core power optimized chiplet (Zen 4c) for 24-cores. You don’t get a bigger GPU going that route though. The chiplet based idea seems a bit odd since I was assuming that the standard IO die will have a very small gpu. I have wondered if the regular IO die is designed to be combined with another for an upscale, intermediate part. That would allow a very cheap Threadripper with up to 4 cpu chiplets and would allow scaling the gpu larger. I have been assuming that Bergamo will be a stacked device of some kind, possibly making use of infinity cache die somehow. If the Zen 4c die is made to be used in that manner, then it may have little to no L3 cache since it would be dependent on stacking. That may not work well without any stacked cache.

Anyway, intel has been leaking/releasing all kinds of info on their future plans while AMD has leaked almost nothing. A combo device has been rumored for Zen 5 using Zen 5 “big” cores and Zen 4 “small” cores. Are we still talking about a Zen 4 only device here? It is possible that AMD changed their plans due to whatever intel is supposedly going to release. Also may be looking at how powerful Apple laptops are and will be.
 
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uzzi38

Platinum Member
Oct 16, 2019
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Ian never stated that slide came from AMD. That slide is not on their investor presentation: PowerPoint Presentation (d1io3yog0oux5.cloudfront.net), nor is it in in their corporate presentation: PowerPoint Presentation (d1io3yog0oux5.cloudfront.net). Furthermore, Dragon Range is not mentioned at all on the AMD website: site:amd.com "dragon range" - Google Search

Seems like Ian either received a fake leak or got the slide from a third-party source. Given that it has a misspelling, I am extremely skeptical of it being real.
It's an official slide given to only a handful of the press from AMD directly. Also, it's very common to find typos in AMD's slides lol.
 

moinmoin

Diamond Member
Jun 1, 2017
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It is possible that AMD changed their plans due to whatever intel is supposedly going to release.
Not really. Every competitor has to run predictions where the market and competition is years in advance. Closer to launch there can't be fundamental changes to the plans anymore, only to aspects of the launch execution like timing (staggering), pricing (segmentation), targeting as well as allocation of chips to different markets.
 

nicalandia

Golden Member
Jan 10, 2019
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Seems like Ian either received a fake leak or got the slide from a third-party source. Given that it has a misspelling, I am extremely skeptical of it being real.
Just so we have this in pixels:

1652269818212.png

AMD claims dragon range has highest core count for a mobile cpu. And what's the highest core count for mobile cpu? It's 16. So DR has 16 cores, simple.
And You can bet their Mobile i9 HX Raptor Lake CPUs will be 24 Cores because Raptor Lake i9s will also be 8P + 16E
 

AtenRa

Lifer
Feb 2, 2009
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AMD is not even Acknowledging Intel's big/Little core.(at least has not acknowledged that recently).
Well the DR could be introduced in Q1 2023 before any new Intel Mobile SKUs that could have more than 16 cores.

Also to note that 12900HX has 16 cores but total threads are only 24 (8+HT +8), on the other hand DR could have 32 threads (16 + HT).
 
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jamescox

Senior member
Nov 11, 2009
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Not really. Every competitor has to run predictions where the market and competition is years in advance. Closer to launch there can't be fundamental changes to the plans anymore, only to aspects of the launch execution like timing (staggering), pricing (segmentation), targeting as well as allocation of chips to different markets.
That has been true in the past, but with AMD’s flexible, modular architecture using MCM and/or stacked die, they can change up their products much more quickly. I am still wondering if the desktop IO die actually has 3 IFOP to keep a 3 cpu chiplet version an option. There are also may be more than one type of cpu chiplet available with the Zen 4c derivative. I have been assuming that it will be a stacked die, so it probably can’t be used with a standard mobile or desktop IO die, but it may not be stacked or they may have built some other modularity features into it allowing it to be used elsewhere. The EFB tech, if used similarly to the way the Apple M1 Ultra is built could add another level of flexibility and modularity by allowing multiple APUs or even multiple IO die to be connected together with very low power consumption.
 
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jamescox

Senior member
Nov 11, 2009
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No. They will go chiplet. Phoenix is not that product though.
They will likely be stacked devices using SoIC or EFB rather than MCMs connected by serdes links. That takes too much power. The chips used in MCMs should never have been called chiplets really. That should have been reserved for packages using at least 2.5D or 3D stacking. An MCM is just multiple chips on a single package although they may be using some more advanced packaging technology in some cases that are not stacking but not a simple MCM either.
 

moinmoin

Diamond Member
Jun 1, 2017
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That has been true in the past, but with AMD’s flexible, modular architecture using MCM and/or stacked die, they can change up their products much more quickly.
It's still true today. Yes, AMD is more flexible using its different multi chips approaches. But those designs still needed to be planned well beforehand to reach that point.

No. They will go chiplet. Phoenix is not that product though.
I'm starting to think Raphael-H alias Dragon Range is the APU gone chiplet which will see further mobile oriented optimizations in later gens. I still doubt it will replace lower cost monolithic APUs though.
 

Anhiel

Junior Member
May 12, 2022
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The way I see it nothing has changed from my own projection like a year ago.

15-24% IPC Increase (Over Zen 3)
8-14% Clock Increase (Over Zen 3)
28-37% ST Perf Increase (Over Zen 3)
So average IPC increase is still (15+24)/2 ~20%. Outliers don't count. You want reliable and generally applicable values.
Only the clock speed is a more sure thing. So topping out at 5.35GHz.
So assuming base clock would be 4.2GHz and all-core boost clock would be 5 to 5.1GHz.
This gives us
ST: (5.35/4.7)*1.2=1.366x
MT: if they are all the same big cores then it's simply (5/4.5)*1.2=1.33x
if they are mixed Zen4 and Zen4c it's complicated so I'll only presume this to apply to 8c+8c configuration
it's complicated to I'll spare you the math details here
then I get 1.19x
 

Anhiel

Junior Member
May 12, 2022
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So back on APU topic.
In part due to rumor:
And if you consider Intel's Meteor Lake the main competitor for Zen4 will feature iGPU with 192 EU that puts it in striking range of RTX 3060M
then AMD would be incompetent and stupid not to see ahead and pull along likewise.

Now to what I see here. Based on computerbase's test of Ryzen 6000 iGPU: AMD Radeon 680M
specifically the TDP available with the new SmartShift Max technology
we see existing limits for CPU 45-80W; iGPU 80-105W
Ryzen 7 6800HS and Ryzen 7 6900HS have same TDP but I prefer 6800HS reference for more reliability
and it fits the leak more, too.
So presuming Zen4 Phoenix N5 35-45W
=> 8c all core clock speed to be the same 4.5 GHz with N5 -30% power => 29.75W
iGPU RDNA3 presuming 12 CU (128-shader CU not RDNA2 64-shader CU)
and based on AMD Radeon RX 6500 XT N6 2.31-2.815GHz RDNA2 16 CU(64-shader CU) 107W => ~2,3756660746 W/CU/GHz
so at 2.0GHz => 114.0319_63_W adjusting for N5 -30% power => 79._81_ W
As can be seen all fairly within current existing comparable SKU's limit.

-------------------------
looking up techpowerup for Nvidia GeForce RTX 3060M
115W version @1702 MHz has 10.94 TFLOPs FP32
=> 60W version @1282 MHz gives ~8.24 TFLOPs FP32
RDNA 3:
12 CU@2GHz ~6.144 TFLOPs FP32
16 CU@2.2GHz ~9 TFLOPs FP32
24 CU@2.2GHz ~13.52 TFLOPs FP32
As can be seen to reach parity the iGPU with 24CU only needs to be clocked at 1.34GHz while the 16CU needs 2.01GHz
 
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nicalandia

Golden Member
Jan 10, 2019
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So back on APU topic.
In part due to rumor:
And if you consider Intel's Meteor Lake the main competitor for Zen4 will feature iGPU with 192 EU that puts it in striking range of RTX 3060M
then AMD would be incompetent and stupid not to see ahead and pull along likewise.
Yeah, good luck to Intel beating AMD RDNA2 Level performance. Intel can't even get their Software/Drivers right.

 
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