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AMD announces move to 32nm in 09
- Thread starter Nemesis 1
- Start date
The speculated timeline for 32nm is...aggressive...given that none of IBM's fab club members are shipping for revenue 45nm product yet; except AMD which has stated they began revenue shipments a month or two ago.
The HK/MG program at IBM must be moving along pretty well for them to be ready to start qual runs on 32nm within 6 months. Impressive if true.
edit: reworded to incorporate the fact that AMD has stated in their Q3 CC they were shipping 45nm product for revenue
The HK/MG program at IBM must be moving along pretty well for them to be ready to start qual runs on 32nm within 6 months. Impressive if true.
edit: reworded to incorporate the fact that AMD has stated in their Q3 CC they were shipping 45nm product for revenue
Nemesis 1
Lifer
Ya I hope AMD can pull this off. I would love to see AMDs 32nm go up against the nehalemC transitor coming to intel @ 32nm.
SANTA CLARA, Calif., June 12, 2006 ? Intel Corporation researchers today disclosed they have developed new technology designed to further extend the company?s leadership in energy-efficient performance.
Intel?s research and development involving new types of transistors has resulted in further development of a tri-gate (3-D) transistor for high-volume manufacturing. Since these transistors greatly improve performance and energy efficiency Intel expects tri-gate technology could become the basic building block for future microprocessors sometime beyond the 45nm process technology node.
SANTA CLARA, Calif., June 12, 2006 ? Intel Corporation researchers today disclosed they have developed new technology designed to further extend the company?s leadership in energy-efficient performance.
Intel?s research and development involving new types of transistors has resulted in further development of a tri-gate (3-D) transistor for high-volume manufacturing. Since these transistors greatly improve performance and energy efficiency Intel expects tri-gate technology could become the basic building block for future microprocessors sometime beyond the 45nm process technology node.
SlowSpyder
Lifer
That's kind of what I thought too, that they should get 45nm out and done well first. 🙂 Maybe this is what kind of benefits they'll be getting from spinning off 'The Foundry Company'.
OOOoooo... you're elite now. Congrats! 🙂
eternalone
Golden Member
WOW 32nm its beautifull. 🙂
Thanks Ocguy31 and SlowSpyder for the kind words, I truly did not see it coming and was actually a tad confused initially by it when some nice folks pointed it out in PM's yesterday. 😱
If this is what I get for not caring then I can't wait to see what happens when I change my handle to Idontgiveacrap 😀
At the manufacturing level there certainly is a human element to the reason why node cadence tends to not go faster than 2 yrs...it really requires some intestinal fortitude to manage a fab in a profitable manner while having large scale technology turnover projects of the likes of a new node creating the entropy and general havoc that it tends to at the human level in their work functions.
But yeah the Foundry Co absolutely must get ballsy crazy aggressive out of the gate if it thinks its going to survive to see 28nm and 22nm clients. It's definitely "do or die" time for the business model, which has actually got to make it pretty exciting to work there for the next 12-18 months. Not so much fun thereafter if they fail to gain critical mass.
I've seen a handful of statements saying Shanghai was shipping/ramping/etc but it's not released for resell yet and I haven't seen any official comments from people at AMD who are responsible for making truthful statements on such. AMD has long burned their bridge with me on the "believe what I say not what I do" press releases.
But I'm not going to quibble the semantics, I'm willing to assume what you say is 100% accurate so I propose modifying the statement to the following:
That's the same 6month gap I was giving them when I said they'd have to start qual runs in 6 months if they are going to hit product ramp in 12.
But even "starting to convert" the lines in a year is not quite the same as being ready to do a qual run...there's prolly another 3-6 months in there even still. Consider that AMD has been talking about 45nm silicon running in their fab for nearly a year now.
http://www.tgdaily.com/content/view/31974/135/
So they'd pretty much have to start converting lines now to be ready in 3-6 months for initial qual runs to be ready 6 months later (after validation, etc) to shift to volume production.
I.e. they'd have to be on the same timeline that Intel is, and let's just be a little bit real about it when all things are considered.
Please go easy on me here, but I need a little help understanding this tick-tock model...
Is it just Intel that uses this or will AMD start too?
Sorry for the newb question... I built my first PC 7 years ago and am currently typing on it now... time for a change. The old Athlon has had it!
Is it just Intel that uses this or will AMD start too?
Sorry for the newb question... I built my first PC 7 years ago and am currently typing on it now... time for a change. The old Athlon has had it!
Welcome to the AT forums! 😀
The tick-tock model as Intel publicly defines it is unique to Intel.
Although tick/tock is what AMD did for 65nm by introducing 65nm to the marketplace with a shrink of their pre-existing 90nm K8 architecture and then subsequently releasing their K10 architecture on the then more mature 65nm process tech a year later.
AMD is expected to also do this at 45nm (Shanghai followed by Istanbul) although it remains to be seen whether Istanbul really turns out to be as much of a tock to Shanghai as Nehalem was to Penryn because we have practically no leaked details about Istanbul.
This is only the second 'tock', so it isn't like there is a lot of experience in figuring what is "better". It would mostly be conjecture. The change in architecture seems more likely to be a larger change than a change in process - but that may not always be the case. I don't speak from experience here - just from observations with die shrinks and architectures in the past - so I apologize if I am incorrect.
I may yet buy an i7 (even though I earlier inferred that I would not), but I probably won't until the second Intel chipset release. That is mostly because I am more wary with the other portions of the platform having bugs than the CPU itself. I would however wait until enough people have had boards running for months before you purchase one, just so you understand what the major bugs in the platform are, and then you can decide whether you can live with those or not.
Of course, the Yorkfield platform is very solid and stable, so if you have no patience to continue to wait then I would suggest that. A solid P45 motherboard, a Q9550 and 4GB of high quality DDR2 can be had for around $500 now. Cheaper if you skimp on some components.
EDIT: I just realized that I misread your question. (I'm sorry🙁) I initially thought that you asked if it would be better to buy a tick or a tock processor. Not sure why I thought that, since your post had nothing to do with that 😱
Thanks for the info and thanks for the welcome! I've been a lurker for a LONG time, in fact, I found a lot of the info I used to help build my first PC (this one) on anandtech. Back then it was my job to keep up on all this as I worked in the software department at a university bookstore while in college. Last couple years I've been completely out of the game. Now it's time to upgrade again! lol.
Thanks again for the welcome and the info!
From my perspective the "tick-tock" model is something the industry has been following for decades - with plenty of exceptions. 🙂
Gordon Moore (co-founder of Intel and of "Moore's Law" fame) once had a list of rules for success. I only vaguely remember them but one of them went something like this "The first rule for career success in a semiconductor company is to never be in charge of an ambitious design to go into a newly built fab" or words to that effect. In other words, when you are putting the finishing touches on a new multi-billion dollar fabrication facility for manufacturing chips, you never want to be in charge of a risky design that's supposed to go into that fab. Because you want to fill that super-expensive fab full of new chips to sell for a huge profit to pay down your investment... not watching the debug engineers scratch their heads as to why the design doesn't work.
That to me is the essence of the tick-tock model - put a low-risk design into a newly built fab (or at least newly retooled fab) so that your new fab can make money right away. Whether companies call it "tick-tock" (no one except Intel does), it's still a well-understood philosophy in the semiconductor business, and companies who ignore it - or try to go for the three-pointer (a new cool design on a new cool process) do so at great risk to their company.
* As always, I am not a spokesperson for my company and my opinions are my own *
Gordon Moore (co-founder of Intel and of "Moore's Law" fame) once had a list of rules for success. I only vaguely remember them but one of them went something like this "The first rule for career success in a semiconductor company is to never be in charge of an ambitious design to go into a newly built fab" or words to that effect. In other words, when you are putting the finishing touches on a new multi-billion dollar fabrication facility for manufacturing chips, you never want to be in charge of a risky design that's supposed to go into that fab. Because you want to fill that super-expensive fab full of new chips to sell for a huge profit to pay down your investment... not watching the debug engineers scratch their heads as to why the design doesn't work.
That to me is the essence of the tick-tock model - put a low-risk design into a newly built fab (or at least newly retooled fab) so that your new fab can make money right away. Whether companies call it "tick-tock" (no one except Intel does), it's still a well-understood philosophy in the semiconductor business, and companies who ignore it - or try to go for the three-pointer (a new cool design on a new cool process) do so at great risk to their company.
* As always, I am not a spokesperson for my company and my opinions are my own *
To be fair, you have to remember that the majority of that delay was a design problem with the first K10s...
Until they had that working just right, they obviously couldn't do a 45nm conversion.
Barcelona will probably end up losing AMD at least 3 full turns of productivity.
That said, I see no reason why they would delay their 32nm chips. You don't need to finish one node to start another...the only downside is that they will lose 9 months of 45nm production, but they can probably hide that in the FabCo changeover anyway.
Not trying to be argumentative but IIRC the claim that a 65nm stepping delay inflicted a 45nm process technology delay is one that has only existed in the speculative circles of forums such as this.
Has AMD ever mentioned 65nm Barelona B3 stepping as the root-cause for 45nm timeline being ~12 months lagging Intels? If it has then it slipped my attention.
Not saying it doesn't stand to reason that the Barcelona fixes in B3 stepping had to be accommodated in Shanghai and that no doubt took time as well, but it wasn't a "re-invent the TLB bug solution wheel" for shanghai either as the bulk of the work was done for the initial fix in K10 (presumably).
However we should be clearer in our use of the terms "45nm conversion". I am speaking to the process technology conversion that happens inside the fab, you appear to be referring to the design/layout/tapeout/validation of a 45nm IC which does not occur inside the fab and usually runs parallel to and independent of the 45nm process technology development cycle (up to the point of validation obviously as then you need physical samples from said process technology to move to next cycle...these are what generally get called qual runs)
A delay in 45nm design of Shanghai (induced by incorporating lessons learned from Barcelona in crisis mode fashion) does not require or necessitate a delay in 45nm process technology development and validation...but a dire shortage of cash and resources most certainly would 😉 (and a shanghai delay from barcelona would most certainly stretch the dollars even thinner and thus delay process technology from that threat vector)
In fact no one does, that's simply how the entire industry operates. Its the same with fab conversions and product mixes within the same fab. It is kind of a working myth that fabs "convert" from one process technology to another.
Truth is they slowly transition as they bring in the necessary equipment (usually <10% new equipment is needed for a new node versus the existing one) and release it to production. A node transition inside an existing and operating fab can take a fully year to really reach the 50/50 mix cross-over point.
It is also common for the same fab to manufacture 3 or 4 nodes at the same time. So long as all the equipment can be shared and the product in question has a cost structure that precludes it from taking advantage of a shrink owing to the layout, mask set, and validation costs then these things have a way of living for nearly a decade.
At TI we were doing 32nm development in a fab that also housed 45nm development, 65nm production, 90nm production, and a handful of lingering low-volume wafer starts of 130nm production...all in the same 300mm fab. It's not just possible, but unless you've got Intel size resources its pretty much impossible to funtionally operate in any other manner.
That said, the reason 32nm would be delayed because of a 45nm delay (and I say this happen at TI with 130nm -> 90nm) is because the 45nm delay can steal resources from the 32nm parallel development efforts as management attempts to deal with cash flow issues in crisis management mode fashion. Same way a Barcelona issue managed to delay Shanghai if our discussion above is to be considered plausible.
Keysplayr
Elite Member
You post a thread about AMD moving to 32nm in 09, then proceed to post an official announcement of Intel's move. I'm going to flat out ask you. Are you in any way shape or form affiliated with Intel? Do you receive any hardware/software for testing/usage/other?
Because if so, I would appreciate a sig update, as I'm sure others would as well.
Nemesis 1
Lifer
The post about 3d gates is nothing more than a look at what intel has in the pipeline . As a comparison to what AMD has in the pipe line. Its all good if both come out with 32nm. at around the same time.
I have been clear on your other question befor. We work on hardware cooling solutions under contract. So yes we get Hardware. But you have neverseen me spout performance figures other than generalizing. I have never broken NDA and my NDA is stricter than most. I do not work for intel . My brother inlaw does. He use to work for another company. We get alsorts of differant hardware. I use the word we . But its my daughters company now. I retired but I still get to play . a little.
Right now my daughter is working( Work s basicly finalized). on soon to be released radiator being brought to market by a company . TO put it in the simplest terms were looking for the best flow to heat dissipatation chaticteristics in a controled setting. Ya see its important for companies to know these things . When using a given fan at a set CFM rating. Flow threw the Rad. and other blocks is critical to the performance of the cooling .
Airflow threw the rad fins. I shouldn't need to mention . . Basicly we look at resistance to flow . and tweak and give our recommendation.
I have seen people do just a tremendious amount of work online with this stuff. The way they approach it is almost a comedy. They dazzel ya with numbers. But come up with no real world solutions. Lets say ya have a 4 loop system . running on 1 pump. how do you normalize each loop. Ya we know. . Because I created a machine to do everthing thats required to do real world testing in real world setting . ON PCs. its perfect and so simple . Must be why its hard to grasp . Its just to easy to comprehend.
Its important to test inline all blocks available. so we can break the numbers down .
I have been clear on your other question befor. We work on hardware cooling solutions under contract. So yes we get Hardware. But you have neverseen me spout performance figures other than generalizing. I have never broken NDA and my NDA is stricter than most. I do not work for intel . My brother inlaw does. He use to work for another company. We get alsorts of differant hardware. I use the word we . But its my daughters company now. I retired but I still get to play . a little.
Right now my daughter is working( Work s basicly finalized). on soon to be released radiator being brought to market by a company . TO put it in the simplest terms were looking for the best flow to heat dissipatation chaticteristics in a controled setting. Ya see its important for companies to know these things . When using a given fan at a set CFM rating. Flow threw the Rad. and other blocks is critical to the performance of the cooling .
Airflow threw the rad fins. I shouldn't need to mention . . Basicly we look at resistance to flow . and tweak and give our recommendation.
I have seen people do just a tremendious amount of work online with this stuff. The way they approach it is almost a comedy. They dazzel ya with numbers. But come up with no real world solutions. Lets say ya have a 4 loop system . running on 1 pump. how do you normalize each loop. Ya we know. . Because I created a machine to do everthing thats required to do real world testing in real world setting . ON PCs. its perfect and so simple . Must be why its hard to grasp . Its just to easy to comprehend.
Its important to test inline all blocks available. so we can break the numbers down .
And some nice low power too.
They've got to address the power consumption side of things if they ever think they are going to fit 12 cores (Magny-Cours) into a single socket and have the GHz remain at a respectable number while keeping the TDP below 140W.
32nm, particularly the HK/MG aspects, will help them nail that.
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